The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Conversores analógico-digitais (ADCs) intercalados no tempo (TI) são frequentemente defendidos como uma solução com eficiência energética para realizar as altas taxas de amostragem exigidas em transceptores de chip único para os esquemas de comunicação emergentes: banda ultralarga, links seriais rápidos, rádio cognitivo e rádio definido por software. No entanto, os efeitos combinados de múltiplas fontes de distorção devido a incompatibilidades de canais (largura de banda, deslocamento, ganho e temporização) afetam severamente o desempenho do sistema e o consumo de energia de um TI ADC e precisam ser considerados desde as fases anteriores do projeto. Neste artigo, o projeto de nível de sistema de TI ADCs é abordado por meio de uma metodologia baseada em plataforma, permitindo a investigação eficaz de diferentes cenários de velocidade/resolução, bem como o impacto do paralelismo na precisão, rendimento, taxa de amostragem, área e consumo de energia. A exploração do espaço de projeto de um ADC de aproximação sucessiva TI é realizada de cima para baixo por meio de simulações de Monte Carlo, explorando modelos comportamentais construídos de baixo para cima após caracterizar implementações viáveis dos principais blocos de construção em um processo CMOS de 90 V de 1 nm. Como resultado, são propostas duas implementações do TI ADC que são capazes de fornecer uma excelente figura de mérito abaixo de 0.15 pJ/etapa de conversão.
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Sergio SAPONARA, Pierluigi NUZZO, Claudio NANI, Geert VAN DER PLAS, Luca FANUCCI, "Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 843-851, June 2009, doi: 10.1587/transele.E92.C.843.
Abstract: Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.843/_p
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@ARTICLE{e92-c_6_843,
author={Sergio SAPONARA, Pierluigi NUZZO, Claudio NANI, Geert VAN DER PLAS, Luca FANUCCI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters},
year={2009},
volume={E92-C},
number={6},
pages={843-851},
abstract={Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.},
keywords={},
doi={10.1587/transele.E92.C.843},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters
T2 - IEICE TRANSACTIONS on Electronics
SP - 843
EP - 851
AU - Sergio SAPONARA
AU - Pierluigi NUZZO
AU - Claudio NANI
AU - Geert VAN DER PLAS
AU - Luca FANUCCI
PY - 2009
DO - 10.1587/transele.E92.C.843
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.
ER -