The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um loop de bloqueio de fase (PLL) de 2.5 fases de 8 GHz é proposto para aplicação de links de transmissão de sistema em chip (SoC) de 10 Gbps. O PLL proposto possui diversos recursos que utilizam novas técnicas de design. A primeira é uma nova célula de atraso variável (VDC) para o oscilador de controle de tensão (VCO). Suas vantagens sobre a célula de atraso convencional são: ampla faixa de frequência de saída e baixa sensibilidade ao ruído com baixo KVCO. A segunda característica é que o PLL consiste em um circuito de autocalibração (SCC) que protege o PLL de variações de processo, tensão e temperatura (PVT). A terceira característica é que o PLL proposto possui uma frequência de saída de 8 fases e também para evitar o efeito potência/terra (P/G) e o efeito de ruído do substrato no PLL, também possui uma baixa frequência de saída de jitter. O PLL é implementado em tecnologia CMOS de 0.13 µm. O jitter de saída do PLL é 2.83 ps (rms) menor que 0.7% do período de saída. A dissipação total de energia é de 21 mW na frequência de saída de 2.5 GHz e a área central é de 0.08 mm2.
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Kuo-Hsing CHENG, Yu-Chang TSAI, Chien-Nan Jimmy LIU, Kai-Wei HONG, Chin-Cheng KUO, "A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 7, pp. 964-972, July 2009, doi: 10.1587/transele.E92.C.964.
Abstract: A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.964/_p
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@ARTICLE{e92-c_7_964,
author={Kuo-Hsing CHENG, Yu-Chang TSAI, Chien-Nan Jimmy LIU, Kai-Wei HONG, Chin-Cheng KUO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application},
year={2009},
volume={E92-C},
number={7},
pages={964-972},
abstract={A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.},
keywords={},
doi={10.1587/transele.E92.C.964},
ISSN={1745-1353},
month={July},}
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TY - JOUR
TI - A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 964
EP - 972
AU - Kuo-Hsing CHENG
AU - Yu-Chang TSAI
AU - Chien-Nan Jimmy LIU
AU - Kai-Wei HONG
AU - Chin-Cheng KUO
PY - 2009
DO - 10.1587/transele.E92.C.964
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2009
AB - A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.
ER -