The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Para aumentar a capacidade e a velocidade de processamento dos switches em fila de entrada (IQ), propusemos uma arquitetura de escalonamento escalável (FSSA). Ao empregar FSSA composto por vários subprogramadores em cascata, switches ou roteadores de alto desempenho em larga escala podem ser realizados sem a limitação de capacidade do dispositivo monolítico. Neste artigo, apresentamos um algoritmo de escalonamento justo denominado FSSA_DI baseado em um FSSA aprimorado onde um esquema de iteração distribuída é empregado, o desempenho do escalonador pode ser melhorado e o tempo de processamento também pode ser reduzido. Os resultados da simulação mostram que o FSSA_DI alcança melhor desempenho em atraso médio e taxa de transferência sob cargas pesadas em comparação com outros algoritmos existentes. Além disso, um prático 64
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Qingsheng HU, Hua-An ZHAO, "Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 279-287, March 2010, doi: 10.1587/transele.E93.C.279.
Abstract: To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.279/_p
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@ARTICLE{e93-c_3_279,
author={Qingsheng HU, Hua-An ZHAO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm},
year={2010},
volume={E93-C},
number={3},
pages={279-287},
abstract={To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64
keywords={},
doi={10.1587/transele.E93.C.279},
ISSN={1745-1353},
month={March},}
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TY - JOUR
TI - Design and Implementation of High-Speed Input-Queued Switches Based on a Fair Scheduling Algorithm
T2 - IEICE TRANSACTIONS on Electronics
SP - 279
EP - 287
AU - Qingsheng HU
AU - Hua-An ZHAO
PY - 2010
DO - 10.1587/transele.E93.C.279
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - To increase both the capacity and the processing speed for input-queued (IQ) switches, we proposed a fair scalable scheduling architecture (FSSA). By employing FSSA comprised of several cascaded sub-schedulers, a large-scale high performance switches or routers can be realized without the capacity limitation of monolithic device. In this paper, we present a fair scheduling algorithm named FSSA_DI based on an improved FSSA where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64
ER -