The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Ao realizar a operação do programa da matriz de memória flash tipo NAND, a célula inibida pelo programa é aplicada por uma tensão positiva na porta, ou seja, linha de palavra (WL) no canal flutuante enquanto a célula do programa é aplicada pela tensão do programa. já que as duas extremidades, linha de seleção de drenagem (DSL) e linha de seleção de fonte (SSL), são ligadas com linha de bits aterrada (BL). Desta forma, é possível o auto-reforço do canal de silício para evitar operações indesejadas do programa. À medida que o dispositivo de memória flash é agressivamente reduzido e a concentração de dopagem do canal é aumentada de acordo, os fenômenos de acoplamento entre WL, porta flutuante (FG)/nó de armazenamento e canal de silício, que são fatores cruciais no esquema de auto-reforço, devem ser investigado mais detalhadamente. Neste trabalho, as dependências do auto-reforço do potencial do canal no comprimento do canal e na concentração de dopagem nos dispositivos de memória flash tipo NAND planar convencional 2-D e 3-D FinFET baseados em silício em massa são investigadas por ambos 2-D e Simulações de dispositivos numéricos 3-D. Como dificilmente existem formas realistas de medir o potencial do canal por sondagem física, acredita-se que a série de trabalhos de simulação ofereça insights práticos na variação do potencial do canal dentro de um dispositivo de memória flash.
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Seongjae CHO, Jung Hoon LEE, Yoon KIM, Jang-Gn YUN, Hyungcheol SHIN, Byung-Gook PARK, "Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 5, pp. 596-601, May 2010, doi: 10.1587/transele.E93.C.596.
Abstract: In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.596/_p
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@ARTICLE{e93-c_5_596,
author={Seongjae CHO, Jung Hoon LEE, Yoon KIM, Jang-Gn YUN, Hyungcheol SHIN, Byung-Gook PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices},
year={2010},
volume={E93-C},
number={5},
pages={596-601},
abstract={In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.},
keywords={},
doi={10.1587/transele.E93.C.596},
ISSN={1745-1353},
month={May},}
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TY - JOUR
TI - Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
T2 - IEICE TRANSACTIONS on Electronics
SP - 596
EP - 601
AU - Seongjae CHO
AU - Jung Hoon LEE
AU - Yoon KIM
AU - Jang-Gn YUN
AU - Hyungcheol SHIN
AU - Byung-Gook PARK
PY - 2010
DO - 10.1587/transele.E93.C.596
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2010
AB - In performing the program operation of the NAND-type flash memory array, the program-inhibited cell is applied by a positive voltage at the gate, i.e., word-line (WL) on the floating channel while the program cell is applied by program voltage as the two ends, drain select line (DSL) and source select line (SSL), are turned on with grounded bit-line (BL). In this manner, the self-boosting of silicon channel to avoid unwanted program operation is made possible. As the flash memory device is aggressively scaled down and the channel doping concentration is increased accordingly, the coupling phenomena among WL, floating gate (FG)/storage node, and silicon channel, which are crucial factors in the self-boosting scheme, should be investigated more thoroughly. In this work, the dependences of self-boosting of channel potential on channel length and doping concentration in the 2-D conventional planar and 3-D FinFET NAND-type flash memory devices based on bulk-silicon are investigated by both 2-D and 3-D numerical device simulations. Since there hardly exists realistic ways of measuring the channel potential by physical probing, the series of simulation works are believed to offer practical insights in the variation of channel potential inside a flash memory device.
ER -