The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um método de proteção ESD de modelo de dispositivo carregado (CDM) no chip para ICs de RF é proposto em um processo de RF de 0.13 µm e avaliado usando um sistema de pulso de linha de transmissão muito rápido (vf-TLP). Principais parâmetros de projeto, como tensão de disparo (Vt1) e a tensão de ruptura de óxido da medição vf-TLP são usadas para projetar circuitos de proteção ESD de entrada para um chip de teste de RF. A caracterização e o comportamento de um retificador controlado por silício acionado por baixa tensão (SCR) usado para proteção contra ESD sob medições vf-TLP também são relatados. Os resultados medidos pelo sistema vf-TLP mostraram que a tensão de disparo diminuiu e a segunda corrente de ruptura aumentou em comparação com os resultados medidos por um sistema TLP padrão de 100 ns. A partir dos testes HBM/CDM, o chip de teste de RF atendeu com sucesso ao nível de resistência ESD de RF solicitado, HBM 1 kV, MM 100 V e CDM 500 V.
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Jae-Young PARK, Jong-Kyu SONG, Dae-Woo KIM, Chang-Soo JANG, Won-Young JUNG, Taek-Soo KIM, "On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 5, pp. 625-630, May 2010, doi: 10.1587/transele.E93.C.625.
Abstract: An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.625/_p
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@ARTICLE{e93-c_5_625,
author={Jae-Young PARK, Jong-Kyu SONG, Dae-Woo KIM, Chang-Soo JANG, Won-Young JUNG, Taek-Soo KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs},
year={2010},
volume={E93-C},
number={5},
pages={625-630},
abstract={An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.},
keywords={},
doi={10.1587/transele.E93.C.625},
ISSN={1745-1353},
month={May},}
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TY - JOUR
TI - On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
T2 - IEICE TRANSACTIONS on Electronics
SP - 625
EP - 630
AU - Jae-Young PARK
AU - Jong-Kyu SONG
AU - Dae-Woo KIM
AU - Chang-Soo JANG
AU - Won-Young JUNG
AU - Taek-Soo KIM
PY - 2010
DO - 10.1587/transele.E93.C.625
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2010
AB - An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.
ER -