The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, é apresentado um front-end analógico de consumo ultrabaixo para etiqueta RFID EPCglobal Classe 1 Geração 2. A etiqueta RFID proposta elimina a necessidade de relógios e contadores de alta frequência usados em etiquetas convencionais, que são os blocos que mais consomem energia. O decodificador sem clock proposto emprega um integrador analógico com uma fonte de corrente adaptativa que fornece uma margem de decodificação uniforme independentemente da taxa de dados e um extrator de frequência de link baseado em um oscilador de relaxamento que gera a frequência usada para retroespalhamento. Um esquema de tensão de alimentação dupla também é empregado para aumentar a eficiência energética da etiqueta. A fim de melhorar a tolerância do circuito proposto às variações ambientais, é proposto um circuito de autocalibração. O circuito front-end analógico RFID proposto é projetado e simulado em CMOS de 0.25 µm, o que mostra que o consumo de energia é reduzido em uma ordem de grandeza em comparação com as etiquetas RFID convencionais, sem perder imunidade às variações ambientais.
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Sung-Jin KIM, Minchang CHO, SeongHwan CHO, "An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 6, pp. 785-795, June 2010, doi: 10.1587/transele.E93.C.785.
Abstract: In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.785/_p
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@ARTICLE{e93-c_6_785,
author={Sung-Jin KIM, Minchang CHO, SeongHwan CHO, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder},
year={2010},
volume={E93-C},
number={6},
pages={785-795},
abstract={In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.},
keywords={},
doi={10.1587/transele.E93.C.785},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder
T2 - IEICE TRANSACTIONS on Electronics
SP - 785
EP - 795
AU - Sung-Jin KIM
AU - Minchang CHO
AU - SeongHwan CHO
PY - 2010
DO - 10.1587/transele.E93.C.785
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.
ER -