The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Uma nova célula de memória dinâmica de acesso aleatório (1T DRAM) de um transistor foi proposta para uma operação de baixa tensão e maior tempo de retenção de dados. A célula 1T DRAM proposta tem três características em comparação com uma célula 1T DRAM convencional: baixa concentração de dopagem corporal, uma estrutura de porta rebaixada e um P + porta poli-Si. Os resultados da simulação mostram que a célula DRAM 1T proposta tem tempo de programa <1-ns e tempo de retenção de dados> 100 ms sob a condição de tensão operacional sub-1-V.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Woojun LEE, Kwangsoo KIM, Woo Young CHOI, "Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 1, pp. 110-115, January 2011, doi: 10.1587/transele.E94.C.110.
Abstract: A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.110/_p
Copiar
@ARTICLE{e94-c_1_110,
author={Woojun LEE, Kwangsoo KIM, Woo Young CHOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time},
year={2011},
volume={E94-C},
number={1},
pages={110-115},
abstract={A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.},
keywords={},
doi={10.1587/transele.E94.C.110},
ISSN={1745-1353},
month={January},}
Copiar
TY - JOUR
TI - Novel 1T DRAM Cell for Low-Voltage Operation and Long Data Retention Time
T2 - IEICE TRANSACTIONS on Electronics
SP - 110
EP - 115
AU - Woojun LEE
AU - Kwangsoo KIM
AU - Woo Young CHOI
PY - 2011
DO - 10.1587/transele.E94.C.110
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2011
AB - A novel one-transistor dynamic random access memory (1T DRAM) cell has been proposed for a low-voltage operation and longer data retention time. The proposed 1T DRAM cell has three features compared with a conventional 1T DRAM cell: low body doping concentration, a recessed gate structure, and a P + poly-Si gate. Simulation results show that the proposed 1T DRAM cell has < 1-ns program time and > 100-ms data retention time under the condition of sub-1-V operating voltage.
ER -