The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Desenvolvemos e aplicamos um novo circuito, denominado circuito de “Nível de tensão autocontrolável (SVL)”, para obter margens expandidas de “leitura” e “gravação” e baixo poder de fuga em um circuito de 90 nm, 2 kbit, seis- transistor CMOS SRAM. Na flutuação de tensão limite de 6σ, a tensão mínima de alimentação da SRAM recém-desenvolvida (dvlp.) para operação de “gravação” foi significativamente reduzida para 0.11 V, menos da metade de uma SRAM convencional equivalente (conv.). A potência de vazamento em espera do dvlp. A SRAM foi de apenas 1.17 µW, o que representa 4.64% da conv. SRAM com tensão de alimentação de 1.0 V. Além disso, a frequência máxima de clock operacional do dvlp. A SRAM era de 138 MHz, o que é 15% maior que (120 MHz) do conv. SRAM em VMM de 0.4 V. Uma sobrecarga de área foi de 0.81% da conv. SRAM.
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Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, "A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 530-538, April 2011, doi: 10.1587/transele.E94.C.530.
Abstract: We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, to achieve an expanded “read” and “write” margins and low leakage power in a 90-nm, 2-kbit, six-transistor CMOS SRAM. At the threshold voltage fluctuation of 6σ, the minimum supply voltage of the newly developed (dvlp.) SRAM for “write” operation was significantly reduced to 0.11 V, less than half that of an equivalent conventional (conv.) SRAM. The standby leakage power of the dvlp. SRAM was only 1.17 µW, which is 4.64% of that of the conv. SRAM at supply voltage of 1.0 V. Moreover, the maximum operating clock frequency of the dvlp. SRAM was 138 MHz, which is 15% higher than that (120 MHz) of the conv. SRAM at VMM of 0.4 V. An area overhead was 0.81% that of the conv. SRAM.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.530/_p
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@ARTICLE{e94-c_4_530,
author={Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM},
year={2011},
volume={E94-C},
number={4},
pages={530-538},
abstract={We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, to achieve an expanded “read” and “write” margins and low leakage power in a 90-nm, 2-kbit, six-transistor CMOS SRAM. At the threshold voltage fluctuation of 6σ, the minimum supply voltage of the newly developed (dvlp.) SRAM for “write” operation was significantly reduced to 0.11 V, less than half that of an equivalent conventional (conv.) SRAM. The standby leakage power of the dvlp. SRAM was only 1.17 µW, which is 4.64% of that of the conv. SRAM at supply voltage of 1.0 V. Moreover, the maximum operating clock frequency of the dvlp. SRAM was 138 MHz, which is 15% higher than that (120 MHz) of the conv. SRAM at VMM of 0.4 V. An area overhead was 0.81% that of the conv. SRAM.},
keywords={},
doi={10.1587/transele.E94.C.530},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM
T2 - IEICE TRANSACTIONS on Electronics
SP - 530
EP - 538
AU - Tadayoshi ENOMOTO
AU - Nobuaki KOBAYASHI
PY - 2011
DO - 10.1587/transele.E94.C.530
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - We developed and applied a new circuit, called the “Self-controllable Voltage Level (SVL)” circuit, to achieve an expanded “read” and “write” margins and low leakage power in a 90-nm, 2-kbit, six-transistor CMOS SRAM. At the threshold voltage fluctuation of 6σ, the minimum supply voltage of the newly developed (dvlp.) SRAM for “write” operation was significantly reduced to 0.11 V, less than half that of an equivalent conventional (conv.) SRAM. The standby leakage power of the dvlp. SRAM was only 1.17 µW, which is 4.64% of that of the conv. SRAM at supply voltage of 1.0 V. Moreover, the maximum operating clock frequency of the dvlp. SRAM was 138 MHz, which is 15% higher than that (120 MHz) of the conv. SRAM at VMM of 0.4 V. An area overhead was 0.81% that of the conv. SRAM.
ER -