The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Uma vantagem de um RLD (dispositivo lógico reconfigurável), como um FPGA (field programmable gate array), é que ele pode ser personalizado após ser fabricado. Devido ao escalonamento agressivo da tecnologia, a densidade do dispositivo está aumentando e, consequentemente, tornou-se um sério problema no consumo de energia. No SoC de sistemas embarcados, o power gating é uma das principais técnicas de redução de potência. No entanto, é difícil adotar RLDs baseados em SRAM devido à alta sobrecarga e à volatilidade da SRAM. Neste artigo, descrevemos um chip TEG (grupo de elementos de teste) de uma tecnologia FeRAM (memória ferroelétrica de acesso aleatório) baseada em lógica reconfigurável. FeRAM traz aos dispositivos lógicos reconfiguráveis a vantagem de ser um verdadeiro power gater. O chip emprega arquitetura de roteamento estilo ilha e usa uma célula lógica de granulação variável como bloco lógico. Um NV-FF (flip-flop não volátil), que contém FeRAM, um FF e circuitos de controle de alimentação, é usado como memórias de configuração e FFs em um bloco lógico. O NV-FF pode transmitir dados entre FeRAM e FF automaticamente quando uma fonte de alimentação é desligada/ligada. Assim, o controle de energia no nível do chip é possível. O tempo de hibernação/restauração é inferior a 1 ms. O chip tem 18
Masahiro IIDA
Masahiro KOGA
Kazuki INOUE
Motoki AMAGASAKI
Yoshinobu ICHIDA
Mitsuro SAJI
Jun IIDA
Toshinori SUEYOSHI
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Masahiro IIDA, Masahiro KOGA, Kazuki INOUE, Motoki AMAGASAKI, Yoshinobu ICHIDA, Mitsuro SAJI, Jun IIDA, Toshinori SUEYOSHI, "A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 548-556, April 2011, doi: 10.1587/transele.E94.C.548.
Abstract: An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.548/_p
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@ARTICLE{e94-c_4_548,
author={Masahiro IIDA, Masahiro KOGA, Kazuki INOUE, Motoki AMAGASAKI, Yoshinobu ICHIDA, Mitsuro SAJI, Jun IIDA, Toshinori SUEYOSHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells},
year={2011},
volume={E94-C},
number={4},
pages={548-556},
abstract={An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18
keywords={},
doi={10.1587/transele.E94.C.548},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
T2 - IEICE TRANSACTIONS on Electronics
SP - 548
EP - 556
AU - Masahiro IIDA
AU - Masahiro KOGA
AU - Kazuki INOUE
AU - Motoki AMAGASAKI
AU - Yoshinobu ICHIDA
AU - Mitsuro SAJI
AU - Jun IIDA
AU - Toshinori SUEYOSHI
PY - 2011
DO - 10.1587/transele.E94.C.548
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - An advantage of an RLD (reconfigurable logic device) such as an FPGA (field programmable gate array) is that it can be customized after being manufactured. Due to the aggressive technology scaling, device density is increasing, and it has become a serious problem in power consumption accordingly. In SoC of embedded systems, power gating is one of the major power reduction techniques. However, it is difficult to adopt SRAM-based RLDs because of the high overhead and SRAM being volatile. In this paper, we describe a TEG (test element group) chip of a reconfigurable logic based FeRAM (ferroelectric random access memory) technology. FeRAM brings reconfigurable logic devices the advantage of being a genuine power gater. The chip employs island-style routing architecture and uses a variable grain logic cell as a logic block. A NV-FF (non-volatile flip-flop), which contains FeRAM, a FF, and power-gating control circuits, is used as both configuration memories and FFs in a logic block. The NV-FF can transmit data between FeRAM and FF automatically when a power source is turned off/on. Thus chip-level power gating is possible. The hibernate/restore time is less than 1 ms. The chip has 18
ER -