The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A sinalização duobinária foi introduzida em comunicações assimétricas de vários chips, como DRAM ou interfaces de exibição, o que permite que uma quantidade controlada de ISI reduza a largura de banda de sinalização em 2/3. Uma equalização sobreamostrada × 2 foi desenvolvida para realizar a sinalização duobinária. Forma de recuperação de clock de taxa de símbolo O sinal duobinário foi desenvolvido para reduzir o consumo de energia dos receptores. Um chip de teste de transmissor Duobinário foi fabricado com processo CMOS de 90 nm. Foi observado um aumento de 3.5 dB na altura dos olhos e um aumento de 1.5 vezes na largura dos olhos.
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Koichi YAMAGUCHI, Masayuki MIZUNO, "A Duobinary Signaling for Asymmetric Multi-Chip Communication" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 619-626, April 2011, doi: 10.1587/transele.E94.C.619.
Abstract: Duobinary signaling has been introduced into asymmetric multi-chip communications such as DRAM or display interfaces, which allows a controlled amount of ISI to reduce signaling bandwidth by 2/3. A × 2 oversampled equalization has been developed to realize Duobinary signaling. Symbol-rate clock recovery form Duobinary signal has been developed to reduce power consumption for receivers. A Duobinary transmitter test chip was fabricated with 90-nm CMOS process. A 3.5 dB increase in eye height and a 1.5 times increase in eye width was observed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.619/_p
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@ARTICLE{e94-c_4_619,
author={Koichi YAMAGUCHI, Masayuki MIZUNO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Duobinary Signaling for Asymmetric Multi-Chip Communication},
year={2011},
volume={E94-C},
number={4},
pages={619-626},
abstract={Duobinary signaling has been introduced into asymmetric multi-chip communications such as DRAM or display interfaces, which allows a controlled amount of ISI to reduce signaling bandwidth by 2/3. A × 2 oversampled equalization has been developed to realize Duobinary signaling. Symbol-rate clock recovery form Duobinary signal has been developed to reduce power consumption for receivers. A Duobinary transmitter test chip was fabricated with 90-nm CMOS process. A 3.5 dB increase in eye height and a 1.5 times increase in eye width was observed.},
keywords={},
doi={10.1587/transele.E94.C.619},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - A Duobinary Signaling for Asymmetric Multi-Chip Communication
T2 - IEICE TRANSACTIONS on Electronics
SP - 619
EP - 626
AU - Koichi YAMAGUCHI
AU - Masayuki MIZUNO
PY - 2011
DO - 10.1587/transele.E94.C.619
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - Duobinary signaling has been introduced into asymmetric multi-chip communications such as DRAM or display interfaces, which allows a controlled amount of ISI to reduce signaling bandwidth by 2/3. A × 2 oversampled equalization has been developed to realize Duobinary signaling. Symbol-rate clock recovery form Duobinary signal has been developed to reduce power consumption for receivers. A Duobinary transmitter test chip was fabricated with 90-nm CMOS process. A 3.5 dB increase in eye height and a 1.5 times increase in eye width was observed.
ER -