The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
No padrão H.264/AVC, muitas técnicas novas, como tamanho de bloco variável (VBS) e quadro de referência múltiplo (MRF), são usadas na parte de estimativa de movimento (ME) para obter desempenho de codificação superior. No entanto, o uso de novas técnicas também causará grande sobrecarga na complexidade computacional, o que leva a problemas na implementação de hardware de baixo consumo de energia. Muitos algoritmos ME rápidos baseados em software são propostos para reduzir a complexidade. Para codificadores conectados em tempo real, o enorme rendimento da estimativa de movimento fracionário (FME) e da estimativa de movimento inteiro (IME) torna o estágio de pipeline uma obrigação. Neste caso, o IME é organizado em um único estágio, o que deteriora a eficiência de muitos algoritmos baseados em software. Com base no fluxo de dados de hardware, este artigo fornece um algoritmo de redução de complexidade que acelera o procedimento ME através de três esquemas. Primeiramente, o algoritmo proposto executa análise de similaridade para detectar MB de modo grande e aplicar encerramento antecipado no estágio IME. Em segundo lugar, para MB normais, o recurso de movimento é extraído após o IME de cada quadro e um esquema de ajuste de faixa de pesquisa baseado em 6 anéis é introduzido para remover posições de pesquisa redundantes. Em terceiro lugar, para MBs que possuem grande recurso de movimento, a diferença de pixels é muito pequena devido ao efeito de desfoque no sensor de vídeo. Portanto, usamos a técnica de subamostragem para reduzir a complexidade computacional para tais MBs. Os resultados experimentais mostram que, em comparação com o algoritmo de busca completa amigável ao hardware, o algoritmo ME rápido proposto pode reduzir de 52.63% a 83.21% do tempo ME com degradação insignificante da qualidade do vídeo. Além disso, como o algoritmo proposto funciona de maneira amigável ao hardware, ele pode ser incorporado em um codificador de vídeo com fio em tempo real de 3 estágios para obter um design de baixo consumo de energia.
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Yiqing HUANG, Qin LIU, Takeshi IKENAGA, "Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 10, pp. 2934-2944, October 2008, doi: 10.1093/ietfec/e91-a.10.2934.
Abstract: In H.264/AVC standard, many new techniques such as variable block size (VBS) and multiple reference frame (MRF) are used in motion estimation (ME) part to achieve superior coding performance. However, the use of new techniques will also cause great burden on computation complexity, which leads to problems in low power hardware implementation. Many software based fast ME algorithms are proposed to reduce complexity. For real-time hardwired encoder, the huge throughput of fractional motion estimation (FME) and integer motion estimation (IME) makes pipeline stage a must. In this case, IME is arranged in a single stage, which deteriorates the efficiency of many software based algorithms. Based on the hardware data flow, this paper provides a complexity reduction algorithm which speeds up ME procedure through three schemes. Firstly, the proposed algorithm executes similarity analysis to detect big mode MB and apply early termination in IME stage. Secondly, for normal MB, motion feature is extracted after IME of each frame and a 6-ring based search range adjustment scheme is introduced to remove redundant search positions. Thirdly, for MBs which have large motion feature, the pixel difference is very small due to the blur effect on video sensor. So, we use subsampling technique to reduce computation complexity for such MBs. Experimental results show that, compared with hardware friendly full search algorithm, the proposed fast ME algorithm can reduce 52.63% to 83.21% ME time with negligible video quality degradation. Furthermore, since the proposed algorithm works in a hardware friendly way, it can be embedded into 3-stage real-time hardwired video encoder to achieve low power design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.10.2934/_p
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@ARTICLE{e91-a_10_2934,
author={Yiqing HUANG, Qin LIU, Takeshi IKENAGA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation},
year={2008},
volume={E91-A},
number={10},
pages={2934-2944},
abstract={In H.264/AVC standard, many new techniques such as variable block size (VBS) and multiple reference frame (MRF) are used in motion estimation (ME) part to achieve superior coding performance. However, the use of new techniques will also cause great burden on computation complexity, which leads to problems in low power hardware implementation. Many software based fast ME algorithms are proposed to reduce complexity. For real-time hardwired encoder, the huge throughput of fractional motion estimation (FME) and integer motion estimation (IME) makes pipeline stage a must. In this case, IME is arranged in a single stage, which deteriorates the efficiency of many software based algorithms. Based on the hardware data flow, this paper provides a complexity reduction algorithm which speeds up ME procedure through three schemes. Firstly, the proposed algorithm executes similarity analysis to detect big mode MB and apply early termination in IME stage. Secondly, for normal MB, motion feature is extracted after IME of each frame and a 6-ring based search range adjustment scheme is introduced to remove redundant search positions. Thirdly, for MBs which have large motion feature, the pixel difference is very small due to the blur effect on video sensor. So, we use subsampling technique to reduce computation complexity for such MBs. Experimental results show that, compared with hardware friendly full search algorithm, the proposed fast ME algorithm can reduce 52.63% to 83.21% ME time with negligible video quality degradation. Furthermore, since the proposed algorithm works in a hardware friendly way, it can be embedded into 3-stage real-time hardwired video encoder to achieve low power design.},
keywords={},
doi={10.1093/ietfec/e91-a.10.2934},
ISSN={1745-1337},
month={October},}
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TY - JOUR
TI - Macroblock Feature Based Complexity Reduction for H.264/AVC Motion Estimation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2934
EP - 2944
AU - Yiqing HUANG
AU - Qin LIU
AU - Takeshi IKENAGA
PY - 2008
DO - 10.1093/ietfec/e91-a.10.2934
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2008
AB - In H.264/AVC standard, many new techniques such as variable block size (VBS) and multiple reference frame (MRF) are used in motion estimation (ME) part to achieve superior coding performance. However, the use of new techniques will also cause great burden on computation complexity, which leads to problems in low power hardware implementation. Many software based fast ME algorithms are proposed to reduce complexity. For real-time hardwired encoder, the huge throughput of fractional motion estimation (FME) and integer motion estimation (IME) makes pipeline stage a must. In this case, IME is arranged in a single stage, which deteriorates the efficiency of many software based algorithms. Based on the hardware data flow, this paper provides a complexity reduction algorithm which speeds up ME procedure through three schemes. Firstly, the proposed algorithm executes similarity analysis to detect big mode MB and apply early termination in IME stage. Secondly, for normal MB, motion feature is extracted after IME of each frame and a 6-ring based search range adjustment scheme is introduced to remove redundant search positions. Thirdly, for MBs which have large motion feature, the pixel difference is very small due to the blur effect on video sensor. So, we use subsampling technique to reduce computation complexity for such MBs. Experimental results show that, compared with hardware friendly full search algorithm, the proposed fast ME algorithm can reduce 52.63% to 83.21% ME time with negligible video quality degradation. Furthermore, since the proposed algorithm works in a hardware friendly way, it can be embedded into 3-stage real-time hardwired video encoder to achieve low power design.
ER -