The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta uma abordagem formal para verificar circuitos aritméticos usando álgebra computacional simbólica. Nosso método descreve circuitos aritméticos diretamente com objetos matemáticos de alto nível baseados em sistemas numéricos ponderados e fórmulas aritméticas. Tal descrição de circuito pode ser efetivamente verificada por técnicas de redução polinomial usando Bases de Grobner. Neste artigo, descrevemos como a álgebra computacional simbólica pode ser usada para descrever e verificar circuitos aritméticos. Os efeitos vantajosos da abordagem proposta são demonstrados através da verificação experimental de alguns circuitos aritméticos, como acumulador múltiplo e filtro FIR. O resultado mostra que a abordagem proposta tem uma possibilidade definitiva de verificar circuitos aritméticos práticos.
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Yuki WATANABE, Naofumi HOMMA, Takafumi AOKI, Tatsuo HIGUCHI, "Arithmetic Circuit Verification Based on Symbolic Computer Algebra" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 10, pp. 3038-3046, October 2008, doi: 10.1093/ietfec/e91-a.10.3038.
Abstract: This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some arithmetic circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.10.3038/_p
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@ARTICLE{e91-a_10_3038,
author={Yuki WATANABE, Naofumi HOMMA, Takafumi AOKI, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Arithmetic Circuit Verification Based on Symbolic Computer Algebra},
year={2008},
volume={E91-A},
number={10},
pages={3038-3046},
abstract={This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some arithmetic circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits.},
keywords={},
doi={10.1093/ietfec/e91-a.10.3038},
ISSN={1745-1337},
month={October},}
Copiar
TY - JOUR
TI - Arithmetic Circuit Verification Based on Symbolic Computer Algebra
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3038
EP - 3046
AU - Yuki WATANABE
AU - Naofumi HOMMA
AU - Takafumi AOKI
AU - Tatsuo HIGUCHI
PY - 2008
DO - 10.1093/ietfec/e91-a.10.3038
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2008
AB - This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some arithmetic circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits.
ER -