The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
À medida que o tamanho do recurso semicondutor diminui, a diafonia devido ao acoplamento capacitivo das interconexões influencia mais seriamente o atraso de propagação do sinal. Além disso, o aumento da frequência operacional enfatiza ainda mais a necessidade de uma análise de temporização mais precisa. Neste artigo, propomos novos modelos de portas para calcular formas de onda de saída de portas sob efeitos de crosstalk, que podem ser usados para estimativa de atraso em nível de porta. Classificamos os modos de operação de dispositivos semicondutores de óxido metálico (MOS) de uma porta em 3 regiões e, a seguir, desenvolvemos modelos lineares simples para cada região. Além disso, apresentamos um método de modelagem de portas não iterativo que é mais eficiente que os métodos iterativos anteriores. Nos experimentos, o método proposto apresenta um erro máximo de 10.70% e um erro médio de 2.63% quando calcula os atrasos de 50% de dois ou três inversores MOS (CMOS) complementares acionando fios paralelos. Em comparação, o método existente apresenta um erro máximo de 25.94% e um erro médio de 3.62% nestas condições.
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Tae Il BAE, Jin Wook KIM, Young Hwan KIM, "New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 12, pp. 3488-3496, December 2008, doi: 10.1093/ietfec/e91-a.12.3488.
Abstract: As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3488/_p
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@ARTICLE{e91-a_12_3488,
author={Tae Il BAE, Jin Wook KIM, Young Hwan KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects},
year={2008},
volume={E91-A},
number={12},
pages={3488-3496},
abstract={As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3488},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - New Gate Models for Gate-Level Delay Calculation under Crosstalk Effects
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3488
EP - 3496
AU - Tae Il BAE
AU - Jin Wook KIM
AU - Young Hwan KIM
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3488
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.
ER -