The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe um sistema de síntese de alto nível para projeto de caminhos de dados de hardwares de processamento digital. O sistema consiste em quatro fases: (1) geração de DFG (gráfico de fluxo de dados), (2) agendamento, (3) ligação de recursos e (4) geração de HDL (linguagem de descrição de hardware). Em (1), o sistema não gera apenas um melhor DFG representando uma determinada descrição comportamental de um hardware, mas mais de um bom DFG representando-o. Em (2) e (3), diversas ferramentas de síntese podem ser incorporadas ao sistema dependendo dos objetivos requeridos. Assim podemos obter mais de um datapath candidato para uma descrição comportamental com sua área e avaliação de desempenho. Em (4), o melhor projeto de caminho de dados é selecionado entre esses candidatos e sua descrição de hardware é gerada. Os resultados experimentais da aplicação do sistema a diversos benchmarks mostram a eficácia e eficiência.
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Nozomu TOGAWA, Takafumi HISAKI, Masao YANAGISAWA, Tatsuo OHTSUKI, "A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2563-2575, December 1998, doi: .
Abstract: This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2563/_p
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@ARTICLE{e81-a_12_2563,
author={Nozomu TOGAWA, Takafumi HISAKI, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration},
year={1998},
volume={E81-A},
number={12},
pages={2563-2575},
abstract={This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2563
EP - 2575
AU - Nozomu TOGAWA
AU - Takafumi HISAKI
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - This paper proposes a high-level synthesis system for datapath design of digital processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.
ER -