The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe um método para reduzir o tempo de troca de contexto utilizando um banco de registros para armazenar contextos de tarefas de trabalho. O custo e o desempenho do hardware foram medidos modelando o banco de registros e o controlador em VHDL. Os seguintes resultados foram obtidos: (1) O controlador pode ser implementado com um custo de hardware muito menor comparado ao do banco de registradores, que é realizado pelo módulo SRAM. (2) O tempo de mudança de contexto pode ser reduzido para menos de 50% em comparação com a implementação de software. (3) A combinação da arquitetura proposta com nosso trabalho anterior (RTOS implementado em HW) nos proporciona um desempenho muito superior de um sistema rígido de tempo real.
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Jun-ichi ITO, Takumi NAKANO, Yoshinori TAKEUCHI, Masaharu IMAI, "Effectiveness of a High Speed Context Switching Method Using Register Bank" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 12, pp. 2661-2667, December 1998, doi: .
Abstract: This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_12_2661/_p
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@ARTICLE{e81-a_12_2661,
author={Jun-ichi ITO, Takumi NAKANO, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Effectiveness of a High Speed Context Switching Method Using Register Bank},
year={1998},
volume={E81-A},
number={12},
pages={2661-2667},
abstract={This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Effectiveness of a High Speed Context Switching Method Using Register Bank
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2661
EP - 2667
AU - Jun-ichi ITO
AU - Takumi NAKANO
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 1998
AB - This paper proposes a method to reduce the context switching time using a register bank to store contexts of working tasks. Hardware cost and performance were measured by modeling the register bank and controller in VHDL. Following results were obtained: (1) The controller can be implemented with a much smaller amount of hardware cost compared to that of the register bank, which is realized by SRAM module. (2) Context switching time can be reduced to less than 50% compared to that by software implementation. (3) Combination of the proposed architecture with our previous work (RTOS implemented in HW) gives us much higher performance of a hard real-time system.
ER -