The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe uma estrutura de circuito totalmente balanceada com ganho de modo comum zero. O ganho de modo comum da estrutura proposta torna-se teoricamente zero com um casamento perfeito do dispositivo. Mesmo que não seja alcançada uma correspondência perfeita do dispositivo, o sinal de modo comum pode ser suficientemente suprimido pelos circuitos de feedback fornecidos com a estrutura. Com base neste conceito, é composto um integrador. Além disso, o conceito pode ser aplicado diretamente ao projeto de um filtro. A aplicação resulta em área de cavacos reduzida. Um exemplo de projeto de filtro de segunda ordem e resultados de simulação verificam a expectativa teórica.
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Moonjae JEONG, Shigetaka TAKAGI, Nobuo FUJII, "Zero Common-Mode Gain Fully Balanced Circuit Structure" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 10, pp. 2210-2218, October 1999, doi: .
Abstract: This paper proposes a fully balanced circuit structure with a zero common-mode gain. The common-mode gain of the proposed structure becomes theoretically zero with a perfect device matching. Even if a perfect device matching is not achieved, the common-mode signal can be sufficiently suppressed by the feedback loops provided with the structure. Based on this concept, an integrator is composed. Furthermore the concept can be directly applied to a filter design. The application results in reduced chip area. A design example of a second-order filter and simulation results verify the theoretical expectation.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_10_2210/_p
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@ARTICLE{e82-a_10_2210,
author={Moonjae JEONG, Shigetaka TAKAGI, Nobuo FUJII, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Zero Common-Mode Gain Fully Balanced Circuit Structure},
year={1999},
volume={E82-A},
number={10},
pages={2210-2218},
abstract={This paper proposes a fully balanced circuit structure with a zero common-mode gain. The common-mode gain of the proposed structure becomes theoretically zero with a perfect device matching. Even if a perfect device matching is not achieved, the common-mode signal can be sufficiently suppressed by the feedback loops provided with the structure. Based on this concept, an integrator is composed. Furthermore the concept can be directly applied to a filter design. The application results in reduced chip area. A design example of a second-order filter and simulation results verify the theoretical expectation.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - Zero Common-Mode Gain Fully Balanced Circuit Structure
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2210
EP - 2218
AU - Moonjae JEONG
AU - Shigetaka TAKAGI
AU - Nobuo FUJII
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 1999
AB - This paper proposes a fully balanced circuit structure with a zero common-mode gain. The common-mode gain of the proposed structure becomes theoretically zero with a perfect device matching. Even if a perfect device matching is not achieved, the common-mode signal can be sufficiently suppressed by the feedback loops provided with the structure. Based on this concept, an integrator is composed. Furthermore the concept can be directly applied to a filter design. The application results in reduced chip area. A design example of a second-order filter and simulation results verify the theoretical expectation.
ER -