The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, é proposta uma nova técnica de otimização de energia específica para aplicação, utilizando uma pequena ROM de instruções que é colocada entre um cache de instruções ou uma memória de programa principal e o núcleo da CPU. Nossa técnica de otimização tem como alvo sistemas embarcados que assumem o seguinte: (i) as memórias de instrução são organizadas por duas memórias no chip, uma memória de programa principal e uma memória de subprograma, (ii) essas duas memórias podem ser ligadas ou desligadas independentemente por uma instrução especial de um processador central, e (iii) um compilador otimiza uma alocação de código objeto nessas duas memórias de modo a minimizar o consumo médio de energia de leitura. Em muitos programas aplicativos, apenas alguns blocos básicos são executados com frequência. Portanto, alocar esses blocos básicos executados com frequência na memória de subprogramas de baixo consumo leva a uma redução significativa de energia. Nossos experimentos com módulos ROM (memória somente leitura) reais criados com tecnologia de processo CMOS de 0.5 µm e programa de codec MPEG2 demonstram reduções significativas de energia de até mais de 50%, na melhor das hipóteses, em relação à abordagem anterior que aplica apenas estrutura de linhas de bits e palavras divididas.
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Tohru ISHIHARA, Hiroto YASUURA, "A Memory Power Optimization Technique for Application Specific Embedded Systems" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2366-2374, November 1999, doi: .
Abstract: In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2366/_p
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@ARTICLE{e82-a_11_2366,
author={Tohru ISHIHARA, Hiroto YASUURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Memory Power Optimization Technique for Application Specific Embedded Systems},
year={1999},
volume={E82-A},
number={11},
pages={2366-2374},
abstract={In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Memory Power Optimization Technique for Application Specific Embedded Systems
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2366
EP - 2374
AU - Tohru ISHIHARA
AU - Hiroto YASUURA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.
ER -