The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Em um sistema de tempo real é necessário reduzir o tempo de resposta a um sinal de interrupção, bem como o tempo de execução de um Sistema Operacional de Tempo Real (RTOS). Para satisfazer este requisito, propusemos um método de implementação de algumas das funcionalidades de um RTOS utilizando hardware. Com base nesta ideia, implementamos um chip VLSI, denominado STRON (silicon TRON: The Realtime Operating system Nucleus), para melhorar o desempenho de um RTOS, onde o chip STRON funciona como uma unidade periférica de qualquer MPU. Neste artigo descrevemos a arquitetura de hardware do chip STRON e os resultados da avaliação de desempenho do RTOS usando o chip STRON. Os seguintes resultados foram obtidos. (1) O chip STRON é implementado em apenas cerca de 10,000 portas quando o número de cada objeto (tarefa, sinalizador de evento, semáforo e interrupção) é 7. (2) O agendador de tarefas pode executar dentro de 8 clocks em um período fixo usando o algoritmo de hardware quando o número de tarefas é 7. (3) A maioria das chamadas básicas do sistema µITRON usando o chip STRON podem ser executadas em um período fixo de alguns microssegundos. (4) O tempo de execução de uma chamada de sistema, medido por um modelo de programa aplicativo multitarefa, pode ser reduzido para cerca de um quinto do que no caso do software RTOS convencional. (5) O desempenho total, incluindo a troca de contexto, é cerca de 2.2 vezes mais rápido que o do software RTOS. Concluímos que o tempo de execução da parte da chamada de sistema implementada pelo chip STRON pode quase ser ignorado, mas a parte do software de interface e a comutação de contexto relacionada à arquitetura de uma MPU influenciam fortemente o desempenho total de um RTOS.
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Takumi NAKANO, Yoshiki KOMATSUDAIRA, Akichika SHIOMI, Masaharu IMAI, "Performance Evaluation of STRON: A Hardware Implementation of a Real-Time OS" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2375-2382, November 1999, doi: .
Abstract: In a real-time system, it is required to reduce the response time to an interrupt signal, as well as the execution time of a Real-Time Operating System (RTOS). In order to satisfy this requirement, we have proposed a method of implementing some of the functionalities of an RTOS using hardware. Based on this idea, we have implemented a VLSI chip, called STRON (silicon TRON: The Realtime Operating system Nucleus), to enhance the performance of an RTOS, where the STRON chip works as a peripheral unit of any MPU. In this paper we describe the hardware architecture of the STRON chip and the performance evaluation results of the RTOS using the STRON chip. The following results were obtained. (1) The STRON chip is implemented in only about 10,000 gates when the number of each object (task, event flag, semaphore, and interrupt) is 7. (2) The task scheduler can execute within 8 clocks in a fixed period using the hardware algorithm when the number of tasks is 7. (3) Most of the basic µITRON system calls using the STRON chip can be executed in a fixed period of a few microseconds. (4) The execution time of a system call, measured by a multitask application program model, can be reduced to about one-fifth that in the case of the conventional software RTOS. (5) The total performance, including context switching, is about 2.2 times faster than that of the software RTOS. We conclude that the execution time of the part of the system call implemented by the STRON chip can almost be ignored, but the part of the interface software and context switching related to the architecture of a MPU strongly influence the total performance of an RTOS.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2375/_p
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@ARTICLE{e82-a_11_2375,
author={Takumi NAKANO, Yoshiki KOMATSUDAIRA, Akichika SHIOMI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Performance Evaluation of STRON: A Hardware Implementation of a Real-Time OS},
year={1999},
volume={E82-A},
number={11},
pages={2375-2382},
abstract={In a real-time system, it is required to reduce the response time to an interrupt signal, as well as the execution time of a Real-Time Operating System (RTOS). In order to satisfy this requirement, we have proposed a method of implementing some of the functionalities of an RTOS using hardware. Based on this idea, we have implemented a VLSI chip, called STRON (silicon TRON: The Realtime Operating system Nucleus), to enhance the performance of an RTOS, where the STRON chip works as a peripheral unit of any MPU. In this paper we describe the hardware architecture of the STRON chip and the performance evaluation results of the RTOS using the STRON chip. The following results were obtained. (1) The STRON chip is implemented in only about 10,000 gates when the number of each object (task, event flag, semaphore, and interrupt) is 7. (2) The task scheduler can execute within 8 clocks in a fixed period using the hardware algorithm when the number of tasks is 7. (3) Most of the basic µITRON system calls using the STRON chip can be executed in a fixed period of a few microseconds. (4) The execution time of a system call, measured by a multitask application program model, can be reduced to about one-fifth that in the case of the conventional software RTOS. (5) The total performance, including context switching, is about 2.2 times faster than that of the software RTOS. We conclude that the execution time of the part of the system call implemented by the STRON chip can almost be ignored, but the part of the interface software and context switching related to the architecture of a MPU strongly influence the total performance of an RTOS.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Performance Evaluation of STRON: A Hardware Implementation of a Real-Time OS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2375
EP - 2382
AU - Takumi NAKANO
AU - Yoshiki KOMATSUDAIRA
AU - Akichika SHIOMI
AU - Masaharu IMAI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - In a real-time system, it is required to reduce the response time to an interrupt signal, as well as the execution time of a Real-Time Operating System (RTOS). In order to satisfy this requirement, we have proposed a method of implementing some of the functionalities of an RTOS using hardware. Based on this idea, we have implemented a VLSI chip, called STRON (silicon TRON: The Realtime Operating system Nucleus), to enhance the performance of an RTOS, where the STRON chip works as a peripheral unit of any MPU. In this paper we describe the hardware architecture of the STRON chip and the performance evaluation results of the RTOS using the STRON chip. The following results were obtained. (1) The STRON chip is implemented in only about 10,000 gates when the number of each object (task, event flag, semaphore, and interrupt) is 7. (2) The task scheduler can execute within 8 clocks in a fixed period using the hardware algorithm when the number of tasks is 7. (3) Most of the basic µITRON system calls using the STRON chip can be executed in a fixed period of a few microseconds. (4) The execution time of a system call, measured by a multitask application program model, can be reduced to about one-fifth that in the case of the conventional software RTOS. (5) The total performance, including context switching, is about 2.2 times faster than that of the software RTOS. We conclude that the execution time of the part of the system call implemented by the STRON chip can almost be ignored, but the part of the interface software and context switching related to the architecture of a MPU strongly influence the total performance of an RTOS.
ER -