The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Sabe-se que o período de clock pode ser menor que o máximo de atrasos de sinal entre registradores se o tempo de chegada do relógio a cada registrador estiver devidamente programado. O algoritmo para projetar uma programação de relógio ideal foi fornecido. Neste artigo, propomos um algoritmo de roteamento de árvore de relógio que realiza um determinado cronograma de relógio usando o modelo de atraso de Elmore. Seguindo a estrutura de incorporação de mesclagem diferida (DME), o algoritmo gera uma topologia da árvore de relógio e determina simultaneamente as localizações e tamanhos dos buffers intermediários. Os resultados experimentais mostraram que este método constrói uma árvore de relógio com comprimento de fio moderado para um layout aleatório de registradores escalonados. Notavelmente, o comprimento do fio necessário para um layout suave de registros programados mostrou ser quase igual ao das árvores de relógio com inclinação zero.
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Kazunori INOUE, Wataru TAKAHASHI, Atsushi TAKAHASHI, Yoji KAJITANI, "Schedule-Clock-Tree Routing for Semi-Synchronous Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2431-2439, November 1999, doi: .
Abstract: It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2431/_p
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@ARTICLE{e82-a_11_2431,
author={Kazunori INOUE, Wataru TAKAHASHI, Atsushi TAKAHASHI, Yoji KAJITANI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Schedule-Clock-Tree Routing for Semi-Synchronous Circuits},
year={1999},
volume={E82-A},
number={11},
pages={2431-2439},
abstract={It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Schedule-Clock-Tree Routing for Semi-Synchronous Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2431
EP - 2439
AU - Kazunori INOUE
AU - Wataru TAKAHASHI
AU - Atsushi TAKAHASHI
AU - Yoji KAJITANI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - It is known that the clock-period can be shorter than the maximum of signal-delays between registers if the clock arrival time to each register is properly scheduled. The algorithm to design an optimal clock-schedule was given. In this paper, we propose a clock-tree routing algorithm that realizes a given clock-schedule using the Elmore-delay model. Following the deferred-merge-embedding (DME) framework, the algorithm generates a topology of the clock-tree and simultaneously determines the locations and sizes of intermediate buffers. The experimental results showed that this method constructs a clock-tree with moderate wire length for a random layout of scheduled registers. Notably, the required wire length for a gentle layout of scheduled registers was shown to be almost equal to that of zero-skew clock-trees.
ER -