The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um transistor MOS de neurônio tem uma porta flutuante e múltiplas portas de entrada que são acopladas capacitivamente à porta flutuante. A redução dramática no número de transistores e interconexões foi alcançada através do emprego do neurônio MOS em projetos de circuitos. Como o eletrodo da porta MOS do neurônio é eletricamente flutuante, não é necessariamente fácil calcular o potencial da porta flutuante usando o simulador de circuito SPICE. A fim de simular circuitos MOS de neurônios de porta flutuante, foi proposto um macromodelo que calcula o potencial da porta flutuante combinando resistências e fontes dependentes de tensão e corrente. Oito tipos de circuitos MOS de neurônios foram projetados e fabricados por um processo CMOS de 1.2 µm de metal duplo de polissilício e dois níveis. Utilizando o SPICE, todos os circuitos MOS dos neurônios foram confirmados para operar corretamente. A tensão limite aparente, vista a partir da porta de entrada no transistor MOS do neurônio de canal n de 2 entradas, é arbitrariamente alterada por um sinal da porta de controle. Inversores MOS de neurônios de múltiplas entradas e circuitos somadores completos MOS de neurônios foram simulados com sucesso. Além disso, a eficácia do macromodelo proposto foi verificada experimentalmente por medições de circuitos fabricados. Os resultados medidos confirmaram que o inversor MOS de neurônios de 3 entradas produz o nível baixo quando o número de portas de entrada às quais um nível alto é aplicado é mais da metade de todas as portas de entrada.
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Tadahiro OCHIAI, Hiroshi HATANO, "A Proposition on Floating Gate Neuron MOS Macromodeling for Device Fabrications" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2485-2491, November 1999, doi: .
Abstract: A neuron MOS transistor has a floating gate and multiple input gates which are capacitively coupling with the floating gate. Dramatic reduction in the number of transistors and interconnections was achieved by employing the neuron MOS in circuit designs. Since the neuron MOS gate electrode is electrically floating, it is not necessarily easy to calculate the floating gate potential using circuit simulator SPICE. In order to simulate floating gate neuron MOS circuits, a macromodel which calculates the floating gate potential combining resistances and dependent voltage and current sources has been proposed. Eight kinds of neuron MOS circuits were designed and fabricated by a double polysilicon two level metal 1.2 µ m CMOS process. Utilizing SPICE, all the neuron MOS circuits were confirmed to operate correctly. The apparent threshold voltage as seen from the input gate in the 2-input n-channel neuron MOS transistor is arbitrarily changed by a control gate signal. Multi-input neuron MOS inverters and neuron MOS full adder circuits have been successfully simulated. Moreover, the effectiveness of the proposed macromodel has been experimentally verified by fabricated circuit measurements. Measured results confirmed that 3-input neuron MOS inverter outputs the low level when the number of input gates to which a high level is applied is more than half of all input gates.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2485/_p
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@ARTICLE{e82-a_11_2485,
author={Tadahiro OCHIAI, Hiroshi HATANO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Proposition on Floating Gate Neuron MOS Macromodeling for Device Fabrications},
year={1999},
volume={E82-A},
number={11},
pages={2485-2491},
abstract={A neuron MOS transistor has a floating gate and multiple input gates which are capacitively coupling with the floating gate. Dramatic reduction in the number of transistors and interconnections was achieved by employing the neuron MOS in circuit designs. Since the neuron MOS gate electrode is electrically floating, it is not necessarily easy to calculate the floating gate potential using circuit simulator SPICE. In order to simulate floating gate neuron MOS circuits, a macromodel which calculates the floating gate potential combining resistances and dependent voltage and current sources has been proposed. Eight kinds of neuron MOS circuits were designed and fabricated by a double polysilicon two level metal 1.2 µ m CMOS process. Utilizing SPICE, all the neuron MOS circuits were confirmed to operate correctly. The apparent threshold voltage as seen from the input gate in the 2-input n-channel neuron MOS transistor is arbitrarily changed by a control gate signal. Multi-input neuron MOS inverters and neuron MOS full adder circuits have been successfully simulated. Moreover, the effectiveness of the proposed macromodel has been experimentally verified by fabricated circuit measurements. Measured results confirmed that 3-input neuron MOS inverter outputs the low level when the number of input gates to which a high level is applied is more than half of all input gates.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Proposition on Floating Gate Neuron MOS Macromodeling for Device Fabrications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2485
EP - 2491
AU - Tadahiro OCHIAI
AU - Hiroshi HATANO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - A neuron MOS transistor has a floating gate and multiple input gates which are capacitively coupling with the floating gate. Dramatic reduction in the number of transistors and interconnections was achieved by employing the neuron MOS in circuit designs. Since the neuron MOS gate electrode is electrically floating, it is not necessarily easy to calculate the floating gate potential using circuit simulator SPICE. In order to simulate floating gate neuron MOS circuits, a macromodel which calculates the floating gate potential combining resistances and dependent voltage and current sources has been proposed. Eight kinds of neuron MOS circuits were designed and fabricated by a double polysilicon two level metal 1.2 µ m CMOS process. Utilizing SPICE, all the neuron MOS circuits were confirmed to operate correctly. The apparent threshold voltage as seen from the input gate in the 2-input n-channel neuron MOS transistor is arbitrarily changed by a control gate signal. Multi-input neuron MOS inverters and neuron MOS full adder circuits have been successfully simulated. Moreover, the effectiveness of the proposed macromodel has been experimentally verified by fabricated circuit measurements. Measured results confirmed that 3-input neuron MOS inverter outputs the low level when the number of input gates to which a high level is applied is more than half of all input gates.
ER -