The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
RSPICE, um simulador de temporização rápida para grandes circuitos MOS digitais, é apresentado neste artigo. Um novo modelo de transistor MOS linear regional baseado em tabela e a solução analítica da primitiva genérica do subcircuito são aplicados para calcular a resposta transitória de circuitos MOS digitais. O efeito de corpo dos transistores de passagem está incluído no modelo MOS e a rede de capacitores flutuantes também pode ser tratada por este subcircuito primitivo. No RSPICE, os transistores MOS com caminho CC são agrupados em um bloco conectado em CC (DCCB), e os DCCBs com caminho de feedback são combinados como um componente fortemente conectado (SCC). RSPICE ordena SCCs pelo algoritmo de Tarjan e simula SCCs ordenados um por um. DCCBs são células básicas no RSPICE e qualquer DCCB pode ser mapeado em um ou mais primitivos de subcircuito. Para calcular analiticamente a resposta transitória dessas primitivas, o RSPICE aproxima os sinais de entrada da primitiva por funções lineares por partes. Para comprometer a precisão da simulação e o tempo de execução, a forma de onda parcial e a convergência de tempo parcial (PWPTC) combinadas com a técnica de janelamento dinâmico são aplicadas para simular SCCs. Outras questões importantes do RSPICE, como partição de circuito, processamento de transistor de passagem e capacitor flutuante, controle de fluxo de simulação e modificação de forma de onda também são discutidas em detalhes. Comparado com HSPICE, o resultado da simulação do RSPICE é muito preciso, com um erro inferior a 3%, mas a velocidade é de 1 a 2 ordens em relação ao HSPICE.
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Xia CAI, Huazhong YANG, Yaowei JIA, Hui WANG, "RSPICE: A Fast and Robust Timing Simulator for Digital MOS VLSI" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2492-2498, November 1999, doi: .
Abstract: RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2492/_p
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@ARTICLE{e82-a_11_2492,
author={Xia CAI, Huazhong YANG, Yaowei JIA, Hui WANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={RSPICE: A Fast and Robust Timing Simulator for Digital MOS VLSI},
year={1999},
volume={E82-A},
number={11},
pages={2492-2498},
abstract={RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - RSPICE: A Fast and Robust Timing Simulator for Digital MOS VLSI
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2492
EP - 2498
AU - Xia CAI
AU - Huazhong YANG
AU - Yaowei JIA
AU - Hui WANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - RSPICE, a fast timing simulator for large digital MOS circuits, is presented in this paper. A new table-based region-wise linear MOS transistor model and the analytical solution of the generic sub-circuit primitive are applied to calculate the transient response of digital MOS circuits. The body effect of pass transistors is included in the MOS model and the floating capacitor network can be handled by this sub-circuit primitive as well. In RSPICE, MOS transistors with a DC path are grouped into a DC-connected block (DCCB), and DCCBs with a feedback path are combined as a strongly connected component (SCC). RSPICE orders SCCs by Tarjan's algorithm and simulates ordered SCCs one by one. DCCBs are basic cells in RSPICE and any DCCB can be mapped into one or more sub-circuit primitives. In order to calculate the transient response of these primitives analytically, RSPICE approximates the input signals of the primitive by piecewise linear functions. To compromise the simulation accuracy and run time, partial waveform and partial time convergent (PWPTC) combined with dynamic windowing technique is applied to simulate SCCs. Other key issues of RSPICE, such as circuit partition, pass-transistor and floating-capacitor processing, simulation-flow control and waveform modification are also discussed in detail. Compared with HSPICE , the simulation result of RSPICE is very accurate with an error less than 3%, but the speed is 1-2 orders over HSPICE.
ER -