The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um algoritmo de síntese de testes de alto nível para escalonamento de operações e alocação de caminhos de dados. A alocação do caminho de dados é alcançada por uma técnica de alocação de equilíbrio de controlabilidade e observabilidade que se baseia na análise de testabilidade no nível de transferência de registro. O escalonamento, por outro lado, é realizado por meio de transformações de reescalonamento que alteram o escalonamento padrão para melhorar a testabilidade. Ao contrário de outros trabalhos em que as tarefas de escalonamento e alocação são realizadas de forma independente, nossa abordagem integra escalonamento e alocação executando-os simultaneamente para que os efeitos do escalonamento e da alocação na testabilidade sejam explorados de forma mais eficaz. Além disso, como os loops sequenciais são amplamente reconhecidos por dificultar o teste de um projeto, uma análise completa (funcional e topológica) do loop é realizada no nível de transferência de registro, a fim de evitar a criação de loop durante o processo de síntese de teste integrado. Com uma variedade de benchmarks de síntese, os resultados experimentais mostram claramente as vantagens do algoritmo proposto.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Tianruo YANG, "The Integrated Scheduling and Allocation of High-Level Test Synthesis" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 1, pp. 145-158, January 1999, doi: .
Abstract: This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_1_145/_p
Copiar
@ARTICLE{e82-a_1_145,
author={Tianruo YANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={The Integrated Scheduling and Allocation of High-Level Test Synthesis},
year={1999},
volume={E82-A},
number={1},
pages={145-158},
abstract={This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.},
keywords={},
doi={},
ISSN={},
month={January},}
Copiar
TY - JOUR
TI - The Integrated Scheduling and Allocation of High-Level Test Synthesis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 145
EP - 158
AU - Tianruo YANG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 1999
AB - This paper presents a high-level test synthesis algorithm for operation scheduling and data path allocation. Data path allocation is achieved by a controllability and observability balance allocation technique which is based on testability analysis at register-transfer level. Scheduling, on other hand, is carried out by rescheduling transformations which change the default scheduling to improve testability. Contrary to other works in which the scheduling and allocation tasks are performed independently, our approach integrates scheduling and allocation by performing them simultaneously so that the effects of scheduling and allocation on testability are exploited more effectively. Additionally, since sequential loops are widely recognized to make a design hard-to-test, a complete (functional and topological) loop analysis is performed at register-transfer level in order to avoid loop creation during the integrated test synthesis process. With a variety of synthesis benchmarks, experimental results show clearly the advantages of the proposed algorithm.
ER -