The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
O deslocamento DC causa degradação do desempenho em sistemas de processamento de sinal, especialmente para aplicações de alta velocidade. É introduzido um novo método de cancelamento de deslocamento que relaxa o requisito de deslocamento dos componentes do circuito no caminho de dados analógicos diferenciais para cerca de 10 vezes maior. Este método move o alvo de ajuste do conversor analógico-digital (ADC) para seu buffer de entrada e ajusta o nível DC da entrada ADC para seu centro antes do cancelamento final do deslocamento. Elimina ajustes pós-produção, como corte de fusíveis, o que aumenta o custo e o TAT na fabricação e nos testes. Os tempos de execução e simulação são reduzidos para 1/9 para menor tempo de acomodação no buffer e com lógica aprimorada. Um circuito automático de calibração de deslocamento rápido é implementado em um pequeno espaço de silício em um canal de unidade de disco rígido (HDD) de alta velocidade com processo CMOS de metal de quatro camadas de 0.25 µm. Os dados medidos mostram que este método funciona de forma eficaz neste sistema.
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Takeo YASUDA, Hajime ANDOH, "Differential Analog Data Path DC Offset Calibration Methods" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 2, pp. 301-306, February 1999, doi: .
Abstract: DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_301/_p
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@ARTICLE{e82-a_2_301,
author={Takeo YASUDA, Hajime ANDOH, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Differential Analog Data Path DC Offset Calibration Methods},
year={1999},
volume={E82-A},
number={2},
pages={301-306},
abstract={DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Differential Analog Data Path DC Offset Calibration Methods
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 301
EP - 306
AU - Takeo YASUDA
AU - Hajime ANDOH
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - DC offset causes performance degradation in signal processing systems especially for high-speed applications. A new offset cancellation method that relaxes the requirement for the offset of the circuit components in the differential analog data path to about 10 times larger is introduced. This method moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the final offset cancellation. It eliminates post-production adjustment such as fuse trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibration circuit is implemented in a small silicon space in a high-speed hard disk drive (HDD) channel with 0.25-µm four-layer metal CMOS process. The measured data show this method works effectively in this system.
ER -