The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve um método eficiente de redução de netlist SPICE, que permite a simulação coletiva de grandes circuitos. O método reduz uma netlist SPICE apenas aos dispositivos que afetam os resultados da simulação. Partes da netlist podem ter seu tamanho significativamente reduzido, surgindo relativamente discrepâncias entre a simulação SPICE original e a simulação SPICE reduzida. O método de redução dos autores é mais geral que trabalhos anteriores, pois reduz circuitos utilizando os recursos dos transistores MOS. De acordo com resultados experimentais, as taxas de redução podem variar de 1/2 a 1/223. Dependendo da redução, o tempo necessário para executar uma simulação SPICE foi reduzido em uma ou duas ordens de magnitude. Usando este método e trabalhando na netlist reduzida, o SPICE poderia até mesmo lidar com netlist para circuitos muito grandes que normalmente não poderia controlar. O erro de simulação entre a simulação SPICE original e a simulação SPICE reduzida foi de cerca de 3.5%.
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Mototaka KURIBAYASHI, Masaaki YAMADA, Hideki TAKEUCHI, Masami MURAKATA, "SCR : SPICE Netlist Reduction Tool" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 3, pp. 417-423, March 1999, doi: .
Abstract: This paper describes an efficient SPICE netlist reduction method, which enables collective simulation of large circuits. The method reduces a SPICE netlist to only those devices which affect the simulation results. Parts of the netlist can be significantly reduced in size, with relatively discrepancies arising between the original SPICE simulation and the reduced SPICE simulation. The authors' reduction method is more general than previous works, since it reduces circuits using the features of MOS transistors. According to experimental results, reduction rates can range from 1/2 to 1/223. Depending on the reduction, the time taken time to run a SPICE simulation was reduced by between one and two oder of magnitude. Using this method and working on the reduced netlist, SPICE could even handle netlist for very large circuits which it could not ordinarily handle. The simulation error between the original SPICE simulation and the reduced SPICE simulation was about 3.5%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_3_417/_p
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@ARTICLE{e82-a_3_417,
author={Mototaka KURIBAYASHI, Masaaki YAMADA, Hideki TAKEUCHI, Masami MURAKATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={SCR : SPICE Netlist Reduction Tool},
year={1999},
volume={E82-A},
number={3},
pages={417-423},
abstract={This paper describes an efficient SPICE netlist reduction method, which enables collective simulation of large circuits. The method reduces a SPICE netlist to only those devices which affect the simulation results. Parts of the netlist can be significantly reduced in size, with relatively discrepancies arising between the original SPICE simulation and the reduced SPICE simulation. The authors' reduction method is more general than previous works, since it reduces circuits using the features of MOS transistors. According to experimental results, reduction rates can range from 1/2 to 1/223. Depending on the reduction, the time taken time to run a SPICE simulation was reduced by between one and two oder of magnitude. Using this method and working on the reduced netlist, SPICE could even handle netlist for very large circuits which it could not ordinarily handle. The simulation error between the original SPICE simulation and the reduced SPICE simulation was about 3.5%.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - SCR : SPICE Netlist Reduction Tool
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 417
EP - 423
AU - Mototaka KURIBAYASHI
AU - Masaaki YAMADA
AU - Hideki TAKEUCHI
AU - Masami MURAKATA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1999
AB - This paper describes an efficient SPICE netlist reduction method, which enables collective simulation of large circuits. The method reduces a SPICE netlist to only those devices which affect the simulation results. Parts of the netlist can be significantly reduced in size, with relatively discrepancies arising between the original SPICE simulation and the reduced SPICE simulation. The authors' reduction method is more general than previous works, since it reduces circuits using the features of MOS transistors. According to experimental results, reduction rates can range from 1/2 to 1/223. Depending on the reduction, the time taken time to run a SPICE simulation was reduced by between one and two oder of magnitude. Using this method and working on the reduced netlist, SPICE could even handle netlist for very large circuits which it could not ordinarily handle. The simulation error between the original SPICE simulation and the reduced SPICE simulation was about 3.5%.
ER -