The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um novo algoritmo de síntese de caminho de dados que leva em consideração simultaneamente três importantes critérios de projeto: testabilidade, área de projeto e tempo total de execução. Definimos uma medida de qualidade na testabilidade de um circuito com base em três regras práticas introduzidas em trabalhos anteriores sobre síntese para testabilidade. Em seguida, desenvolvemos um algoritmo de síntese de refinamento gradual que realiza as tarefas de escalonamento e alocação de forma integrada. Resultados experimentais para benchmark e outros exemplos de circuitos mostram que fomos capazes de melhorar significativamente a testabilidade dos circuitos com muito pouca sobrecarga na área de projeto e no tempo de execução.
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Taewhan KIM, Ki-Seok CHUNG, C. L. LIU, "A Stepwise Refinement Synthesis of Digital Systems for Testability Enhancement" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 6, pp. 1070-1081, June 1999, doi: .
Abstract: This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tasks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we were able to enhance the testability of circuits significantly with very little overheads on design area and execution time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_1070/_p
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@ARTICLE{e82-a_6_1070,
author={Taewhan KIM, Ki-Seok CHUNG, C. L. LIU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Stepwise Refinement Synthesis of Digital Systems for Testability Enhancement},
year={1999},
volume={E82-A},
number={6},
pages={1070-1081},
abstract={This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tasks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we were able to enhance the testability of circuits significantly with very little overheads on design area and execution time.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - A Stepwise Refinement Synthesis of Digital Systems for Testability Enhancement
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1070
EP - 1081
AU - Taewhan KIM
AU - Ki-Seok CHUNG
AU - C. L. LIU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tasks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we were able to enhance the testability of circuits significantly with very little overheads on design area and execution time.
ER -