The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um algoritmo evolutivo é usado para evoluir um circuito digital que calcula uma função hash simples mapeando um espaço de endereço de 16 bits em um espaço de 8 bits. A tecnologia alvo é FPGA, onde o espaço de busca do algoritmo é composto pelas funções combinacionais computadas pelas células e pelas interconexões entre as células. A técnica evolutiva foi aplicada a cinco topologias de interconexão diferentes, especificadas por gráficos de vizinhança. Este circuito é facilmente aplicável ao projeto de conjunto-associativo memórias cache. Possível uso da abordagem evolucionária apresentada no artigo para On-line o ajuste da função durante a operação do cache também é discutido.
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Ernesto DAMIANI, Valentino LIBERALI, Andrea G. B. TETTAMANZI, "FPGA-Based Hash Circuit Synthesis with Evolutionary Algorithms" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 9, pp. 1888-1896, September 1999, doi: .
Abstract: An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. The evolutionary technique has been applied to five different interconnection topologies, specified by neighbourhood graphs. This circuit is readily applicable to the design of set-associative cache memories. Possible use of the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_9_1888/_p
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@ARTICLE{e82-a_9_1888,
author={Ernesto DAMIANI, Valentino LIBERALI, Andrea G. B. TETTAMANZI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={FPGA-Based Hash Circuit Synthesis with Evolutionary Algorithms},
year={1999},
volume={E82-A},
number={9},
pages={1888-1896},
abstract={An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. The evolutionary technique has been applied to five different interconnection topologies, specified by neighbourhood graphs. This circuit is readily applicable to the design of set-associative cache memories. Possible use of the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - FPGA-Based Hash Circuit Synthesis with Evolutionary Algorithms
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1888
EP - 1896
AU - Ernesto DAMIANI
AU - Valentino LIBERALI
AU - Andrea G. B. TETTAMANZI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 1999
AB - An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. The evolutionary technique has been applied to five different interconnection topologies, specified by neighbourhood graphs. This circuit is readily applicable to the design of set-associative cache memories. Possible use of the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed.
ER -