The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Propomos uma memória funcional para adição (FMA), que é uma lógica LSI mesclada com memória. É uma memória e também um processador paralelo SIMD. Para minimizar a área, um elemento de precessão (PE) consiste em várias palavras DRAM e uma ALU serial de bits. A ALU possui uma funcionalidade de adição bit a bit. Este artigo descreve dois LSIs experimentais FMA. Um é para uso geral e o outro é para correspondência completa de blocos de pesquisa de compactação de imagem. Estimamos que um processo de 0.18 µm realize 57,000 PEs em um processo de 50 mm.2 morrer, alcançando 205 GOPS com potência de 1.36 W.
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Kazutoshi KOBAYASHI, Masanao YAMAOKA, Yukifumi KOBAYASHI, Hidetoshi ONODERA, Keikichi TAMARU, "Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2400-2408, December 2000, doi: .
Abstract: We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2400/_p
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@ARTICLE{e83-a_12_2400,
author={Kazutoshi KOBAYASHI, Masanao YAMAOKA, Yukifumi KOBAYASHI, Hidetoshi ONODERA, Keikichi TAMARU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition},
year={2000},
volume={E83-A},
number={12},
pages={2400-2408},
abstract={We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2400
EP - 2408
AU - Kazutoshi KOBAYASHI
AU - Masanao YAMAOKA
AU - Yukifumi KOBAYASHI
AU - Hidetoshi ONODERA
AU - Keikichi TAMARU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - We propose a functional memory for addition (FMA), which is a memory-merged logic LSI. It is a memory as well as a SIMD parallel processor. To minimize the area, a precessing element (PE) consists of several DRAM words and a bit-serial ALU. The ALU has a functionality of addition bit by bit. This paper describes two FMA experimental LSIs. One is for general purpose, and the other is for full search block matching of image compression. We estimate that a 0.18 µm process realizes 57,000 PEs in a 50 mm2 die, achieving 205 GOPS under 1.36 W power.
ER -