The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Como função de um sistema cada vez mais complexo, a reutilização de IP (Propriedade Intelectual) é a tendência do estilo de design de sistemas. Os designers precisam avaliar o desempenho e os recursos de cada bloco IP candidato que pode ser usado em seu projeto, enquanto os provedores de IP esperam manter em segredo a estrutura de seus blocos IP. Um modelo de potência de nível IP é um modelo que utiliza apenas as estatísticas de entrada primária como parâmetros e não revela nenhuma informação sobre os tamanhos dos transistores ou a estrutura do circuito. Este artigo propõe um novo método para construção de modelo de potência adequado para blocos de circuitos de nível IP. É um método de seleção de pontos nominais para modelos de potência baseados em sensibilidades de potência. Ao analisar a relação entre o consumo dinâmico de potência dos circuitos CMOS e as estatísticas do sinal de entrada, é proposta uma diretriz para seleção do ponto nominal. Da nossa análise, o primeiro ponto nominal é selecionado para minimizar o erro médio de estimativa e outros dois pontos nominais são selecionados para minimizar o erro máximo de estimativa. Nossos resultados experimentais em vários circuitos de benchmark mostram a eficácia do método proposto. A precisão média da estimativa é alcançada em 5.78% das simulações de nível de transistor. O método proposto pode ser aplicado para construir um ambiente de estimativa de energia em nível de sistema sem revelar o conteúdo dos blocos IP internos. Assim, é um método promissor para a construção de modelos de potência em nível IP.
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Heng-Liang HUANG, Jiing-Yuan LIN, Wen-Zen SHEN, Jing-Yang JOU, "A New Method for Constructing IP Level Power Model Based on Power Sensitivity" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2431-2438, December 2000, doi: .
Abstract: As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2431/_p
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@ARTICLE{e83-a_12_2431,
author={Heng-Liang HUANG, Jiing-Yuan LIN, Wen-Zen SHEN, Jing-Yang JOU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A New Method for Constructing IP Level Power Model Based on Power Sensitivity},
year={2000},
volume={E83-A},
number={12},
pages={2431-2438},
abstract={As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A New Method for Constructing IP Level Power Model Based on Power Sensitivity
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2431
EP - 2438
AU - Heng-Liang HUANG
AU - Jiing-Yuan LIN
AU - Wen-Zen SHEN
AU - Jing-Yang JOU
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - As the function of a system getting more complex, IP (Intellectual Property) reusing is the trend of system design style. Designers need to evaluate the performance and features of every candidate IP block that can be used in their design, while IP providers hope to keep the structure of their IP blocks a secret. An IP level power model is a model that takes only the primary input statistics as parameters and does not reveal any information about the sizes of the transistors or the structure of the circuit. This paper proposes a new method for constructing power model that is suitable for IP level circuit blocks. It is a nominal point selection method for power models based on power sensitivities. By analyzing the relationship between the dynamic power consumption of CMOS circuits and their input signal statistics, a guideline of selecting the nominal point is proposed. From our analysis, the first nominal point is selected to minimize the average estimation error and two other nominal points are selected to minimize the maximum estimation error. Our experimental results on a number of benchmark circuits show the effectiveness of the proposed method. Average estimation accuracy within 5.78% of transistor level simulations is achieved. The proposed method can be applied to build a system level power estimation environment without revealing the contents of the IP blocks inside. Thereby, it is a promising method for IP level power model construction.
ER -