The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um algoritmo de particionamento de circuito de melhoria iterativo baseado em temporização sob restrições de atraso de caminho para o modelo de atraso geral. O algoritmo proposto é uma extensão do método Fiduccia & Mattheyses (FM) para lidar com restrições de atraso de caminho e consiste nas fases de agrupamento e melhoria iterativa. Na primeira fase, reduzimos o tamanho de um determinado circuito, com um novo algoritmo de agrupamento para obter uma partição em um curto tempo de computação. Em seguida, a fase de melhoria iterativa baseada no método FM é aplicada e, em seguida, um novo algoritmo de remoção de violação de temporização baseado em caminho também é executado para remover todas as violações de temporização. A partir de resultados experimentais para benchmarks ISCAS89, demonstramos que o algoritmo proposto pode produzir as partições que mais satisfazem as restrições de tempo.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Jun'ichiro MINAMI, Tetsushi KOIDE, Shin'ichi WAKABAYASHI, "An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 12, pp. 2569-2576, December 2000, doi: .
Abstract: This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_12_2569/_p
Copiar
@ARTICLE{e83-a_12_2569,
author={Jun'ichiro MINAMI, Tetsushi KOIDE, Shin'ichi WAKABAYASHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints},
year={2000},
volume={E83-A},
number={12},
pages={2569-2576},
abstract={This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.},
keywords={},
doi={},
ISSN={},
month={December},}
Copiar
TY - JOUR
TI - An Iterative Improvement Circuit Partitioning Algorithm under Path Delay Constraints
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2569
EP - 2576
AU - Jun'ichiro MINAMI
AU - Tetsushi KOIDE
AU - Shin'ichi WAKABAYASHI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2000
AB - This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.
ER -