The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve um circuito de recuperação de dados com sobreamostragem composto por um loop analógico bloqueado com atraso e uma lógica de decisão digital. A nova técnica de sobreamostragem é baseada no circuito de loop bloqueado por atraso bloqueado para vários períodos de clock, em vez de um único período de clock, o que gera uma resolução de tempo menor que o atraso de porta da cadeia de atraso. A lógica digital para recuperação de dados foi implementada partindo do pressuposto de que não há desvio de frequência que prejudique o centro dos dados adquiridos. O chip foi fabricado usando tecnologia CMOS de 0.6 µm. O chip foi testado com dados de entrada NRZ de 1.0 Gb/s com clock de 125 MHz e recupera os dados de entrada serial em oito fluxos de saída de 125 Mb/s.
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Jun-Young PARK, Jin-Ku KANG, "A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 6, pp. 1100-1105, June 2000, doi: .
Abstract: This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_6_1100/_p
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@ARTICLE{e83-a_6_1100,
author={Jun-Young PARK, Jin-Ku KANG, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method},
year={2000},
volume={E83-A},
number={6},
pages={1100-1105},
abstract={This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - A 1.0 Gbps CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1100
EP - 1105
AU - Jun-Young PARK
AU - Jin-Ku KANG
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2000
AB - This paper describes an oversampling data recovery circuit composed of an analog delay locked loop and a digital decision logic. The novel oversampling technique is based on the delay locked loop circuit locked to multiple clock periods rather than a single clock period, which generates the timing resolution less than the gate delay of the delay chain. The digital logic for data recovery was implemented with the assumption that there is no frequency deviation that hurts the center of acquired data. The chip has been fabricated using 0.6 µm CMOS technology. The chip has been tested at 1.0 Gb/s NRZ input data with 125 MHz clock and recovers the serial input data into eight 125 Mb/s output stream.
ER -