The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta a implementação de um circuito de clock e recuperação de dados (CDR) de baixa potência de 3 V e multitaxa de 156, 622 e 1244 Mbps para transceptor de comunicações ópticas usando uma nova arquitetura de recuperação de clock paralelo baseada em PLL de bomba de carga dupla. O circuito projetado recupera sinais de clock de oito fases que são um oitavo da frequência do sinal de entrada. Enquanto o sistema típico usa o método que compara os dados de entrada com o relógio recuperado, o circuito proposto compara dados de entrada atrasados de 1/2 bit com os dados seriais gerados pelos sinais de relógio de oito fases recuperados. A vantagem do circuito é que a implementação é fácil, pois cada subbloco possui um oitavo da frequência do sinal de dados de entrada. Além disso, como o circuito funciona a um oitavo da frequência dos dados de entrada, ele dissipa menos energia do que o circuito de recuperação CMOS convencional. Os resultados da simulação mostram que este circuito de recuperação pode funcionar com dissipação de potência inferior a 40 mW com uma única alimentação de 3 V. Todas as simulações são baseadas na tecnologia HYUNDAI 0.65 µm N-Well CMOS duplo-poli duplo-metal.
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Hae-Moon SEO, Chang-Gene WOO, Sang-Won OH, Sung-Wook JUNG, Pyung CHOI, "A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 8, pp. 1720-1727, August 2000, doi: .
Abstract: This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_8_1720/_p
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@ARTICLE{e83-a_8_1720,
author={Hae-Moon SEO, Chang-Gene WOO, Sang-Won OH, Sung-Wook JUNG, Pyung CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications},
year={2000},
volume={E83-A},
number={8},
pages={1720-1727},
abstract={This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.},
keywords={},
doi={},
ISSN={},
month={August},}
Copiar
TY - JOUR
TI - A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1720
EP - 1727
AU - Hae-Moon SEO
AU - Chang-Gene WOO
AU - Sang-Won OH
AU - Sung-Wook JUNG
AU - Pyung CHOI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2000
AB - This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.
ER -