The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
As restrições de limite do planejamento VLSI exigem que um conjunto de blocos seja colocado ao longo dos limites do chip. Assim, este conjunto de blocos pode ser adjacente a blocos de E/S para comunicação externa. Além disso, esses blocos são mantidos afastados da área central para não bloquearem o roteamento interno. No artigo, desenvolvemos um algoritmo de planejamento VLSI com restrições de limite usando uma representação Corner Block List (CBL). Identificamos as condições necessárias e suficientes da representação CBL para as restrições de contorno. Projetamos uma abordagem de tempo linear para examinar as condições e formular uma função de penalidade para punir a violação da restrição. Um processo de recozimento simulado é adotado para otimizar a planta baixa. Experimentos em benchmarks MCNC mostram resultados promissores.
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Yuchun MA, Xianlong HONG, Sheqin DONG, Yici CAI, Chung-Kuan CHENG, Jun GU, "VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 11, pp. 2697-2704, November 2001, doi: .
Abstract: Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_11_2697/_p
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@ARTICLE{e84-a_11_2697,
author={Yuchun MA, Xianlong HONG, Sheqin DONG, Yici CAI, Chung-Kuan CHENG, Jun GU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation},
year={2001},
volume={E84-A},
number={11},
pages={2697-2704},
abstract={Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2697
EP - 2704
AU - Yuchun MA
AU - Xianlong HONG
AU - Sheqin DONG
AU - Yici CAI
AU - Chung-Kuan CHENG
AU - Jun GU
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2001
AB - Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.
ER -