The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É proposto um procedimento de otimização em coeficientes moduladores Delta-sigma (ΔΣ) de ordem superior. O procedimento é baseado no método de julgamento de estabilidade do modulador ΔΣ de ordem superior. A especificação da aplicação pode ser satisfeita com o método proposto. Os exemplos de moduladores de 4ª ordem são ilustrados. Os coeficientes otimizados e os resultados da simulação do modelo de comportamento demonstraram que esta metodologia é adequada para o projeto de conversor ΔΣ AD de ordem superior. A tolerância de coeficientes de até 2% é permitida para implementação de capacitor chaveado, com degradação não superior a 3.5 dB SNR (Signal to Noise Ratio). Os coeficientes otimizados melhoram 2 a 3 bits da resolução do modulador em relação ao algoritmo proposto anteriormente e permanecem o limite de entrada estável, satisfazendo os requisitos do projeto original.
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Yikui ZHANG, Etsuro HAYAHARA, Satoshi HIRANO, "Higher Order Delta-Sigma AD Converter with Optimized Stable Coefficients" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 3, pp. 813-819, March 2001, doi: .
Abstract: Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_3_813/_p
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@ARTICLE{e84-a_3_813,
author={Yikui ZHANG, Etsuro HAYAHARA, Satoshi HIRANO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Higher Order Delta-Sigma AD Converter with Optimized Stable Coefficients},
year={2001},
volume={E84-A},
number={3},
pages={813-819},
abstract={Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Higher Order Delta-Sigma AD Converter with Optimized Stable Coefficients
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 813
EP - 819
AU - Yikui ZHANG
AU - Etsuro HAYAHARA
AU - Satoshi HIRANO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2001
AB - Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.
ER -