The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Projetamos um microprocessador RISC de 32 bits com funcionalidade DSP de ponto fixo de 16/32 bits. Este processador, denominado YD-RISC, combina a funcionalidade de microprocessador de uso geral e processador de sinal digital (DSP) usando os princípios de design do computador com conjunto de instruções reduzido (RISC). Possui unidades funcionais para operação aritmética, processamento digital de sinais (DSP) e acesso à memória. Eles operam em paralelo para remover ciclos de parada após DSP ou instruções de carregamento/armazenamento, que geralmente precisam de um ou mais ciclos de latência de emissão além do primeiro ciclo de emissão. O alto desempenho foi alcançado com essas unidades funcionais paralelas, ao mesmo tempo que se adotava uma sofisticada estrutura de pipeline de cinco estágios. A unidade DSP em pipeline pode executar uma instrução de multiplicação-acumulação (MAC) de 32 bits ou de multiplicação complexa de 16 bits a cada um ou dois ciclos através de duas instruções de 17-b.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Byung In MOON, Dong Ryul RYU, Jong Wook HONG, Tae Young LEE, Sangook MOON, Yong Surk LEE, "A 32-bit RISC Microprocessor with DSP Functionality: Rapid Prototyping" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 5, pp. 1339-1347, May 2001, doi: .
Abstract: We have designed a 32-bit RISC microprocessor with 16-/32-bit fixed-point DSP functionality. This processor, called YD-RISC, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline structure. The pipelined DSP unit can execute one 32-bit multiply-accumulate (MAC) or 16-bit complex multiply instruction every one or two cycles through two 17-b
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_5_1339/_p
Copiar
@ARTICLE{e84-a_5_1339,
author={Byung In MOON, Dong Ryul RYU, Jong Wook HONG, Tae Young LEE, Sangook MOON, Yong Surk LEE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 32-bit RISC Microprocessor with DSP Functionality: Rapid Prototyping},
year={2001},
volume={E84-A},
number={5},
pages={1339-1347},
abstract={We have designed a 32-bit RISC microprocessor with 16-/32-bit fixed-point DSP functionality. This processor, called YD-RISC, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline structure. The pipelined DSP unit can execute one 32-bit multiply-accumulate (MAC) or 16-bit complex multiply instruction every one or two cycles through two 17-b
keywords={},
doi={},
ISSN={},
month={May},}
Copiar
TY - JOUR
TI - A 32-bit RISC Microprocessor with DSP Functionality: Rapid Prototyping
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1339
EP - 1347
AU - Byung In MOON
AU - Dong Ryul RYU
AU - Jong Wook HONG
AU - Tae Young LEE
AU - Sangook MOON
AU - Yong Surk LEE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 2001
AB - We have designed a 32-bit RISC microprocessor with 16-/32-bit fixed-point DSP functionality. This processor, called YD-RISC, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline structure. The pipelined DSP unit can execute one 32-bit multiply-accumulate (MAC) or 16-bit complex multiply instruction every one or two cycles through two 17-b
ER -