The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Para filtros digitais FIR de fase linear de baixa complexidade que possuem coeficientes expressos como código de dígito assinado canônico (CSD), é proposto um método de projeto para impor ganho CC de potência de dois. O nível do sinal de saída pode ser facilmente compensado com o da entrada, de modo que a cascata de muitos estágios não cause erros de ganho, que são prejudiciais, por exemplo, em sistemas de medição de alta precisão. O projeto é formulado como um problema de otimização com restrições de resposta de magnitude. A programação linear inteira modificada para códigos CSD é resolvida pelo método branch andbound. O exemplo de projeto mostra a eficácia do filtro obtido em comparação com os filtros CSD existentes. Além disso, é proposto um método de avaliação da área para implementação do filtro em field programmable gate array (FPGA). O exemplo de implementação mostra que o caminho crítico mínimo é obtido com apenas um pequeno aumento na área da matriz.
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Mitsuru YAMADA, Akinori NISHIHARA, "Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 8, pp. 1997-2003, August 2001, doi: .
Abstract: For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose power-of-two DC gain is proposed. Output signal level can easily be compensated to that of input so that cascading many stages do not cause any gain errors, which are harmful in, for example, high precision measurement systems. The design is formulated as an optimization problem with magnitude response constraints. The integer linear programming modified for CSD codes is solved by the branch and bound method. The design example shows the effectiveness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field programmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the die area.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_8_1997/_p
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@ARTICLE{e84-a_8_1997,
author={Mitsuru YAMADA, Akinori NISHIHARA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path},
year={2001},
volume={E84-A},
number={8},
pages={1997-2003},
abstract={For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose power-of-two DC gain is proposed. Output signal level can easily be compensated to that of input so that cascading many stages do not cause any gain errors, which are harmful in, for example, high precision measurement systems. The design is formulated as an optimization problem with magnitude response constraints. The integer linear programming modified for CSD codes is solved by the branch and bound method. The design example shows the effectiveness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field programmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the die area.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC Gain and Their FPGA Implementation for Minimum Critical Path
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1997
EP - 2003
AU - Mitsuru YAMADA
AU - Akinori NISHIHARA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2001
AB - For low-complexity linear-phase FIR digital filters which have coefficients expressed as canonic signed digit (CSD) code, a design method to impose power-of-two DC gain is proposed. Output signal level can easily be compensated to that of input so that cascading many stages do not cause any gain errors, which are harmful in, for example, high precision measurement systems. The design is formulated as an optimization problem with magnitude response constraints. The integer linear programming modified for CSD codes is solved by the branch and bound method. The design example shows the effectiveness of the obtained filter in comparison with existing CSD filters. Also, an evaluation method for the area to implement the filter into field programmable gate array (FPGA) is proposed. The implementation example shows that the minimum critical path is obtained with only a little increase in the die area.
ER -