The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe um método de geração de compilador para PEAS-III (Practical Environment for ASIP development), que é um ambiente de desenvolvimento de processador configurável para sistemas embarcados específicos de domínio de aplicação. Usando o sistema PEAS-III, não apenas a descrição HDL de um processador alvo, mas também de seu compilador alvo pode ser gerada. Portanto, os ciclos de execução e o consumo dinâmico de energia podem ser avaliados rapidamente. Dois processadores e seus derivados foram projetados usando o sistema PEAS-III no experimento. Os resultados experimentais mostram que os compromissos entre área, desempenho e consumo de energia dos processadores foram analisados em cerca de doze horas e o processador ideal foi selecionado sob as restrições de projeto usando compiladores e processadores gerados.
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Shinsuke KOBAYASHI, Kentaro MITA, Yoshinori TAKEUCHI, Masaharu IMAI, "A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2586-2595, December 2002, doi: .
Abstract: This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2586/_p
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@ARTICLE{e85-a_12_2586,
author={Shinsuke KOBAYASHI, Kentaro MITA, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors},
year={2002},
volume={E85-A},
number={12},
pages={2586-2595},
abstract={This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2586
EP - 2595
AU - Shinsuke KOBAYASHI
AU - Kentaro MITA
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.
ER -