The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, propomos um método eficiente de geração de testes de alto nível para circuitos assíncronos. A geração do teste é baseada no nível de especificação, principalmente no Signal Transition Graph (STG), que é uma espécie de método de especificação para circuitos assíncronos. Definimos um modelo de falha de alto nível, denominado modelo de falha de transição de estado único (STF) no STG. Os padrões de teste para STFs são gerados com base no Stable State Graph (SSG), que pode ser derivado diretamente do STG. O espaço de estados explorado na geração de testes é bastante reduzido e, portanto, o custo de geração de testes é pequeno em termos de tempo de execução. Para melhorar a cobertura de faltas no nível do portão, também propusemos um modelo STF estendido (ESTF) com informações adicionais no nível do portão. Resultados experimentais mostram que o teste gerado para STFs alcança alta cobertura de faltas com baixo custo para faltas únicas do seu circuito de nível de porta sintetizado correspondente. O teste gerado para ESTFs atinge maior cobertura de falhas com o mesmo benchmark em custo de maior tempo de execução. Além disso, também propusemos uma geração de teste trifásico com base nos métodos propostos acima. Uma geração de teste eficaz é implementada em três fases: 3) geração de teste para STFs, 3) geração de teste para ESTFs e 1) geração de teste usando um método assíncrono de passagem de máquina de produto. Os resultados experimentais também mostram que a geração de teste trifásica proposta alcança maior cobertura de faltas no custo de maior tempo de execução.
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Eunjung OH, Soo-Hyun KIM, Dong-Ik LEE, Ho-Yong CHOI, "High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2674-2683, December 2002, doi: .
Abstract: In this paper, we have proposed an efficient high-level test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph (STG), which is a kind of specification method for asynchronous circuits. We define a high-level fault model, called a single State Transition Fault (STF) model on STG. Test patterns for STFs are generated based on Stable State Graph (SSG), which can be derived from STG directly. The state space explored in test generation is greatly reduced and hence the test generation cost is small in terms of execution time. To enhance the fault coverage at gate-level, we have also proposed an extended STF (ESTF) model with additional gate-level information. Experimental results show that the generated test for STFs achieves high fault coverage with low cost for single stuck-at faults of its corresponding synthesized gate-level circuit. The generated test for ESTFs attains higher fault coverage with same benchmark in cost of longer execution time. Further, we have also proposed a 3-phase test generation based on the above proposed methods. An effective test generation is implemented by 3-phase: 1) test generation for STFs, 2) test generation for ESTFs, and 3) test generation using an asynchronous product machine traversal method. Experimental results also show that the proposed 3-phase test generation achieves higher fault coverage in cost of longer execution time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2674/_p
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@ARTICLE{e85-a_12_2674,
author={Eunjung OH, Soo-Hyun KIM, Dong-Ik LEE, Ho-Yong CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph},
year={2002},
volume={E85-A},
number={12},
pages={2674-2683},
abstract={In this paper, we have proposed an efficient high-level test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph (STG), which is a kind of specification method for asynchronous circuits. We define a high-level fault model, called a single State Transition Fault (STF) model on STG. Test patterns for STFs are generated based on Stable State Graph (SSG), which can be derived from STG directly. The state space explored in test generation is greatly reduced and hence the test generation cost is small in terms of execution time. To enhance the fault coverage at gate-level, we have also proposed an extended STF (ESTF) model with additional gate-level information. Experimental results show that the generated test for STFs achieves high fault coverage with low cost for single stuck-at faults of its corresponding synthesized gate-level circuit. The generated test for ESTFs attains higher fault coverage with same benchmark in cost of longer execution time. Further, we have also proposed a 3-phase test generation based on the above proposed methods. An effective test generation is implemented by 3-phase: 1) test generation for STFs, 2) test generation for ESTFs, and 3) test generation using an asynchronous product machine traversal method. Experimental results also show that the proposed 3-phase test generation achieves higher fault coverage in cost of longer execution time.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - High-Level Test Generation for Asynchronous Circuits from Signal Transition Graph
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2674
EP - 2683
AU - Eunjung OH
AU - Soo-Hyun KIM
AU - Dong-Ik LEE
AU - Ho-Yong CHOI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - In this paper, we have proposed an efficient high-level test generation method for asynchronous circuits. The test generation is based on specification level, especially on Signal Transition Graph (STG), which is a kind of specification method for asynchronous circuits. We define a high-level fault model, called a single State Transition Fault (STF) model on STG. Test patterns for STFs are generated based on Stable State Graph (SSG), which can be derived from STG directly. The state space explored in test generation is greatly reduced and hence the test generation cost is small in terms of execution time. To enhance the fault coverage at gate-level, we have also proposed an extended STF (ESTF) model with additional gate-level information. Experimental results show that the generated test for STFs achieves high fault coverage with low cost for single stuck-at faults of its corresponding synthesized gate-level circuit. The generated test for ESTFs attains higher fault coverage with same benchmark in cost of longer execution time. Further, we have also proposed a 3-phase test generation based on the above proposed methods. An effective test generation is implemented by 3-phase: 1) test generation for STFs, 2) test generation for ESTFs, and 3) test generation using an asynchronous product machine traversal method. Experimental results also show that the proposed 3-phase test generation achieves higher fault coverage in cost of longer execution time.
ER -