The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um transportador de corrente CMOS de segunda geração (CCII) que consiste em um estágio de entrada diferencial de canal n e p complementar trilho a trilho para a entrada de tensão, um estágio push-pull classe AB para a entrada de corrente e um estágio de corrente push-pull classe AB para a entrada de corrente. espelhos para as saídas de corrente. O CCII foi implementado usando um processo CMOS de n poços de 0.6 µm de duplo poli triplo metal, para confirmar seu funcionamento experimentalmente. Um protótipo de chip atinge um balanço de trilho a trilho
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Takashi KURASHINA, Satomi OGAWA, Kenzo WATANABE, "A CMOS Rail-to-Rail Current Conveyor" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2894-2900, December 2002, doi: .
Abstract: This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary n- and p-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors for the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 µm n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2894/_p
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@ARTICLE{e85-a_12_2894,
author={Takashi KURASHINA, Satomi OGAWA, Kenzo WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A CMOS Rail-to-Rail Current Conveyor},
year={2002},
volume={E85-A},
number={12},
pages={2894-2900},
abstract={This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary n- and p-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors for the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 µm n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - A CMOS Rail-to-Rail Current Conveyor
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2894
EP - 2900
AU - Takashi KURASHINA
AU - Satomi OGAWA
AU - Kenzo WATANABE
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary n- and p-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors for the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 µm n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing
ER -