The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
O projeto aproximado do multiplicador é uma técnica eficaz para melhorar o desempenho do hardware ao custo da perda de precisão. Os multiplicadores aproximados atuais são em sua maioria baseados em ASIC e dedicados a uma aplicação específica. Em contraste, o FPGA tem sido uma escolha atraente para muitas aplicações devido ao seu alto desempenho, reconfigurabilidade e rápido desenvolvimento. Este artigo apresenta uma nova metodologia para projetar multiplicadores aproximados, empregando estruturas baseadas em FPGA (principalmente tabelas de consulta e cadeias de transporte). A área e a latência são significativamente reduzidas aplicando a aproximação nos resultados de transporte e cortando o caminho de propagação de transporte no multiplicador. Além disso, exploramos multiplicadores de ordem superior no espaço arquitetônico usando nossos multiplicadores aproximados de tamanho pequeno propostos como módulos elementares. Para diferentes requisitos de hardware de precisão, são discutidas oito configurações para multiplicador aproximado de 8×8. Em termos de distância média de erro relativo (MRED), o erro do multiplicador 8×8 proposto é tão baixo quanto 1.06%. Comparado com o multiplicador exato, nosso projeto proposto pode reduzir a área em 43.66% e a potência em 24.24%. A redução da latência do caminho crítico é de até 29.50%. O projeto do multiplicador proposto tem uma melhor compensação entre precisão e hardware do que outros projetos com precisão comparável. Além disso, o processamento de nitidez de imagem é usado para avaliar a eficiência de multiplicadores aproximados na aplicação.
Yi GUO
Waseda University
Heming SUN
the Waseda Research Institute for Science and Engineering,PRESTO
Ping LEI
Waseda University
Shinji KIMURA
Waseda University
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Yi GUO, Heming SUN, Ping LEI, Shinji KIMURA, "Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules" in IEICE TRANSACTIONS on Fundamentals,
vol. E103-A, no. 9, pp. 1054-1062, September 2020, doi: 10.1587/transfun.2019KEP0002.
Abstract: Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2019KEP0002/_p
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@ARTICLE{e103-a_9_1054,
author={Yi GUO, Heming SUN, Ping LEI, Shinji KIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules},
year={2020},
volume={E103-A},
number={9},
pages={1054-1062},
abstract={Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.},
keywords={},
doi={10.1587/transfun.2019KEP0002},
ISSN={1745-1337},
month={September},}
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TY - JOUR
TI - Approximate FPGA-Based Multipliers Using Carry-Inexact Elementary Modules
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1054
EP - 1062
AU - Yi GUO
AU - Heming SUN
AU - Ping LEI
AU - Shinji KIMURA
PY - 2020
DO - 10.1587/transfun.2019KEP0002
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E103-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2020
AB - Approximate multiplier design is an effective technique to improve hardware performance at the cost of accuracy loss. The current approximate multipliers are mostly ASIC-based and are dedicated for one particular application. In contrast, FPGA has been an attractive choice for many applications because of its high performance, reconfigurability, and fast development round. This paper presents a novel methodology for designing approximate multipliers by employing the FPGA-based fabrics (primarily look-up tables and carry chains). The area and latency are significantly reduced by applying approximation on carry results and cutting the carry propagation path in the multiplier. Moreover, we explore higher-order multipliers on architectural space by using our proposed small-size approximate multipliers as elementary modules. For different accuracy-hardware requirements, eight configurations for approximate 8×8 multiplier are discussed. In terms of mean relative error distance (MRED), the error of the proposed 8×8 multiplier is as low as 1.06%. Compared with the exact multiplier, our proposed design can reduce area by 43.66% and power by 24.24%. The critical path latency reduction is up to 29.50%. The proposed multiplier design has a better accuracy-hardware tradeoff than other designs with comparable accuracy. Moreover, image sharpening processing is used to assess the efficiency of approximate multipliers on application.
ER -