The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A análise das degradações de atraso induzidas pelo envelhecimento de osciladores de anel (ROs) é uma maneira eficaz de detectar matrizes de portas programáveis em campo (FPGAs) recicladas. No entanto, requer um grande número de medições de RO para todos os FPGAs antes do envio, o que aumenta os custos de medição. Propomos um método de detecção de FPGA reciclado econômico usando uma técnica estatística de caracterização de desempenho chamada sonda virtual (VP) baseada em detecção compactada. A técnica VP permite a previsão precisa da variação do processo espacial das frequências de RO em uma matriz usando um número muito pequeno de medições de RO de amostra. Usando a variação de frequência prevista como supervisor, o modelo de aprendizado de máquina classifica os FPGAs alvo como reciclados ou novos. Através de experimentos conduzidos utilizando 50 FPGAs comerciais, demonstramos que o método proposto atinge 90% de redução de custos para medições de RO, preservando a precisão da detecção. Além disso, um algoritmo de máquina de vetores de suporte de classe única foi usado para classificar FPGAs alvo com precisão de detecção de cerca de 94%.
Foisal AHMED
Nara Institute of Science and Technology (NAIST)
Michihiro SHINTANI
Nara Institute of Science and Technology (NAIST)
Michiko INOUE
Nara Institute of Science and Technology (NAIST)
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Foisal AHMED, Michihiro SHINTANI, Michiko INOUE, "Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework" in IEICE TRANSACTIONS on Fundamentals,
vol. E103-A, no. 9, pp. 1045-1053, September 2020, doi: 10.1587/transfun.2019KEP0014.
Abstract: Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2019KEP0014/_p
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@ARTICLE{e103-a_9_1045,
author={Foisal AHMED, Michihiro SHINTANI, Michiko INOUE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework},
year={2020},
volume={E103-A},
number={9},
pages={1045-1053},
abstract={Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.},
keywords={},
doi={10.1587/transfun.2019KEP0014},
ISSN={1745-1337},
month={September},}
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TY - JOUR
TI - Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1045
EP - 1053
AU - Foisal AHMED
AU - Michihiro SHINTANI
AU - Michiko INOUE
PY - 2020
DO - 10.1587/transfun.2019KEP0014
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E103-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2020
AB - Analyzing aging-induced delay degradations of ring oscillators (ROs) is an effective way to detect recycled field-programmable gate arrays (FPGAs). However, it requires a large number of RO measurements for all FPGAs before shipping, which increases the measurement costs. We propose a cost-efficient recycled FPGA detection method using a statistical performance characterization technique called virtual probe (VP) based on compressed sensing. The VP technique enables the accurate prediction of the spatial process variation of RO frequencies on a die by using a very small number of sample RO measurements. Using the predicted frequency variation as a supervisor, the machine-learning model classifies target FPGAs as either recycled or fresh. Through experiments conducted using 50 commercial FPGAs, we demonstrate that the proposed method achieves 90% cost reduction for RO measurements while preserving the detection accuracy. Furthermore, a one-class support vector machine algorithm was used to classify target FPGAs with around 94% detection accuracy.
ER -