The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo formula o tempo de atraso mínimo da linha de palavra (WL) com pulsos de pré-ênfase para projetar a largura do pulso como uma função da tensão de overdrive para grandes matrizes de memória, como 3D NAND. A teoria do circuito para uma única linha RC apenas com capacitância para terra e apenas com capacitância de acoplamento, bem como um caso geral em que as linhas RC têm aterramento e capacitância de acoplamento é discutida para fornecer uma largura de pulso de pré-ênfase ideal para minimizar o tempo de atraso. A teoria é expandida para incluir os casos em que a resistência do driver de linha RC não é desprezivelmente pequena. As fórmulas de tempo de atraso mínimo de uma única linha de atraso RC e linhas RC de acoplamento capacitivo estavam em boa concordância (ou seja, com erro de 5%) com a medição. Com esta pesquisa, os projetistas de circuitos podem estimar uma largura de pulso de pré-ênfase ideal e o tempo de atraso para uma linha RC na fase inicial do projeto.
Kazuki MATSUYAMA
Shizuoka University
Toru TANZAWA
Shizuoka University
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Kazuki MATSUYAMA, Toru TANZAWA, "A Circuit Analysis of Pre-Emphasis Pulses for RC Delay Lines" in IEICE TRANSACTIONS on Fundamentals,
vol. E104-A, no. 6, pp. 912-926, June 2021, doi: 10.1587/transfun.2020EAP1083.
Abstract: This paper formulates minimal word-line (WL) delay time with pre-emphasis pulses to design the pulse width as a function of the overdrive voltage for large memory arrays such as 3D NAND. Circuit theory for a single RC line only with capacitance to ground and that only with coupling capacitance as well as a general case where RC lines have both grounded and coupling capacitance is discussed to provide an optimum pre-emphasis pulse width to minimize the delay time. The theory is expanded to include the cases where the resistance of the RC line driver is not negligibly small. The minimum delay time formulas of a single RC delay line and capacitive coupling RC lines was in good agreement (i.e. within 5% error) with measurement. With this research, circuit designers can estimate an optimum pre-emphasis pulse width and the delay time for an RC line in the initial design phase.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020EAP1083/_p
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@ARTICLE{e104-a_6_912,
author={Kazuki MATSUYAMA, Toru TANZAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Circuit Analysis of Pre-Emphasis Pulses for RC Delay Lines},
year={2021},
volume={E104-A},
number={6},
pages={912-926},
abstract={This paper formulates minimal word-line (WL) delay time with pre-emphasis pulses to design the pulse width as a function of the overdrive voltage for large memory arrays such as 3D NAND. Circuit theory for a single RC line only with capacitance to ground and that only with coupling capacitance as well as a general case where RC lines have both grounded and coupling capacitance is discussed to provide an optimum pre-emphasis pulse width to minimize the delay time. The theory is expanded to include the cases where the resistance of the RC line driver is not negligibly small. The minimum delay time formulas of a single RC delay line and capacitive coupling RC lines was in good agreement (i.e. within 5% error) with measurement. With this research, circuit designers can estimate an optimum pre-emphasis pulse width and the delay time for an RC line in the initial design phase.},
keywords={},
doi={10.1587/transfun.2020EAP1083},
ISSN={1745-1337},
month={June},}
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TY - JOUR
TI - A Circuit Analysis of Pre-Emphasis Pulses for RC Delay Lines
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 912
EP - 926
AU - Kazuki MATSUYAMA
AU - Toru TANZAWA
PY - 2021
DO - 10.1587/transfun.2020EAP1083
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E104-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 2021
AB - This paper formulates minimal word-line (WL) delay time with pre-emphasis pulses to design the pulse width as a function of the overdrive voltage for large memory arrays such as 3D NAND. Circuit theory for a single RC line only with capacitance to ground and that only with coupling capacitance as well as a general case where RC lines have both grounded and coupling capacitance is discussed to provide an optimum pre-emphasis pulse width to minimize the delay time. The theory is expanded to include the cases where the resistance of the RC line driver is not negligibly small. The minimum delay time formulas of a single RC delay line and capacitive coupling RC lines was in good agreement (i.e. within 5% error) with measurement. With this research, circuit designers can estimate an optimum pre-emphasis pulse width and the delay time for an RC line in the initial design phase.
ER -