The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um IC amplificador de potência (PA) de alta eficiência de back-off de banda de 26 GHz com polarização controlada adaptativamente e circuitos de carga em CMOS SOI de 45 nm. Um FET de 4 pilhas é empregado para aumentar a potência de saída e superar o problema de baixa tensão de ruptura do MOSFET escalonado. O circuito de polarização adaptativa é revisado e o circuito de carga adaptativa que consiste em um circuito inversor e indutores baseados em transformador é descrito em detalhes. O desempenho medido do PA IC é totalmente mostrado neste artigo. O PA IC exibe uma potência de saída saturada de 20.5dBm e um pico de eficiência de potência adicionada (PAE) de até 39.4% a uma tensão de alimentação de 4.0V. Além disso, o PA IC exibiu um excelente ITRS FoM de 82.0dB.
Toshihiko YOSHIMASU
Waseda University
Mengchu FANG
Waseda University
Tsuyoshi SUGIURA
the Samsung R&D Institute Japan
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Toshihiko YOSHIMASU, Mengchu FANG, Tsuyoshi SUGIURA, "A 26-GHz-Band High Back-Off Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Bias and Load Circuits in 45-nm CMOS SOI" in IEICE TRANSACTIONS on Fundamentals,
vol. E104-A, no. 2, pp. 477-483, February 2021, doi: 10.1587/transfun.2020GCP0012.
Abstract: This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0dB.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020GCP0012/_p
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@ARTICLE{e104-a_2_477,
author={Toshihiko YOSHIMASU, Mengchu FANG, Tsuyoshi SUGIURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 26-GHz-Band High Back-Off Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Bias and Load Circuits in 45-nm CMOS SOI},
year={2021},
volume={E104-A},
number={2},
pages={477-483},
abstract={This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0dB.},
keywords={},
doi={10.1587/transfun.2020GCP0012},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - A 26-GHz-Band High Back-Off Efficiency Stacked-FET Power Amplifier IC with Adaptively Controlled Bias and Load Circuits in 45-nm CMOS SOI
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 477
EP - 483
AU - Toshihiko YOSHIMASU
AU - Mengchu FANG
AU - Tsuyoshi SUGIURA
PY - 2021
DO - 10.1587/transfun.2020GCP0012
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E104-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2021
AB - This paper presents a 26-GHz-band high back-off efficiency power amplifier (PA) IC with adaptively controlled bias and load circuits in 45-nm CMOS SOI. A 4-stacked-FET is employed to increase the output power and to conquer the low breakdown voltage issue of scaled MOSFET. The adaptive bias circuit is reviewed and the adaptive load circuit which consists of an inverter circuit and transformer-based inductors is described in detail. The measured performance of the PA IC is fully shown in this paper. The PA IC exhibits a saturated output power of 20.5dBm and a peak power-added-efficiency (PAE) as high as 39.4% at a supply voltage of 4.0V. Moreover, the PA IC has exhibited an excellent ITRS FoM of 82.0dB.
ER -