The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, propomos quatro métodos de otimização durante a conversão de Register Transfer Level (RTL) de modelos RTL síncronos em modelos RTL assíncronos. A modularização dos recursos do caminho de dados e o uso de flip-flops D apropriados reduzem a área do circuito. A fixação do sinal de controle dos multiplexadores e a inserção de travas para os recursos do caminho de dados reduzem o consumo dinâmico de energia. No experimento, avaliamos o efeito dos métodos de otimização propostos. A combinação de todos os métodos de otimização poderia reduzir o consumo de energia em 21.9% em média em comparação com aqueles sem os métodos de otimização propostos.
Shogo SEMBA
University of Aizu
Hiroshi SAITO
University of Aizu
Masato TATSUOKA
Socionext Inc.
Katsuya FUJIMURA
Socionext Inc.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Shogo SEMBA, Hiroshi SAITO, Masato TATSUOKA, Katsuya FUJIMURA, "Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models" in IEICE TRANSACTIONS on Fundamentals,
vol. E103-A, no. 12, pp. 1417-1426, December 2020, doi: 10.1587/transfun.2020VLP0004.
Abstract: In this paper, we propose four optimization methods during the Register Transfer Level (RTL) conversion from synchronous RTL models into asynchronous RTL models. The modularization of data-path resources and the use of appropriate D flip-flops reduce the circuit area. Fixing the control signal of the multiplexers and inserting latches for the data-path resources reduce the dynamic power consumption. In the experiment, we evaluated the effect of the proposed optimization methods. The combination of all optimization methods could reduce the energy consumption by 21.9% on average compared to the ones without the proposed optimization methods.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2020VLP0004/_p
Copiar
@ARTICLE{e103-a_12_1417,
author={Shogo SEMBA, Hiroshi SAITO, Masato TATSUOKA, Katsuya FUJIMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models},
year={2020},
volume={E103-A},
number={12},
pages={1417-1426},
abstract={In this paper, we propose four optimization methods during the Register Transfer Level (RTL) conversion from synchronous RTL models into asynchronous RTL models. The modularization of data-path resources and the use of appropriate D flip-flops reduce the circuit area. Fixing the control signal of the multiplexers and inserting latches for the data-path resources reduce the dynamic power consumption. In the experiment, we evaluated the effect of the proposed optimization methods. The combination of all optimization methods could reduce the energy consumption by 21.9% on average compared to the ones without the proposed optimization methods.},
keywords={},
doi={10.1587/transfun.2020VLP0004},
ISSN={1745-1337},
month={December},}
Copiar
TY - JOUR
TI - Optimization Methods during RTL Conversion from Synchronous RTL Models to Asynchronous RTL Models
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1417
EP - 1426
AU - Shogo SEMBA
AU - Hiroshi SAITO
AU - Masato TATSUOKA
AU - Katsuya FUJIMURA
PY - 2020
DO - 10.1587/transfun.2020VLP0004
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E103-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2020
AB - In this paper, we propose four optimization methods during the Register Transfer Level (RTL) conversion from synchronous RTL models into asynchronous RTL models. The modularization of data-path resources and the use of appropriate D flip-flops reduce the circuit area. Fixing the control signal of the multiplexers and inserting latches for the data-path resources reduce the dynamic power consumption. In the experiment, we evaluated the effect of the proposed optimization methods. The combination of all optimization methods could reduce the energy consumption by 21.9% on average compared to the ones without the proposed optimization methods.
ER -