The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Em aplicações de Internet das Coisas (IoT), os sistemas em chip (SoCs) com processadores incorporados são amplamente utilizados. Como processador embarcado, o RISC-V, que não tem licença e possui um conjunto de instruções extensível, está recebendo atenção. No entanto, projetar tais processadores embarcados requer um enorme esforço para alcançar uma microarquitetura altamente eficiente em termos de desempenho, consumo de energia e área de circuito, bem como a verificação do projeto de execução de software complexo, incluindo sistemas operacionais modernos como o Linux. Neste artigo, propomos um método para descrever diretamente a estrutura RTL de um processador RISC-V em pipeline com memórias cache, uma unidade de gerenciamento de memória (MMU) e uma interface de barramento AXI usando a linguagem C++. Este modelo C++ de processador em pipeline serve como um simulador funcional do núcleo RISC-V completo, enquanto nossa estrutura C2RTL traduz o modelo C++ do processador em uma descrição RTL com precisão de ciclo no modelo Verilog-HDL e C equivalente a RTL. Nossa metodologia de projeto de processador usando a estrutura C2RTL é única em comparação com outras metodologias existentes porque tanto os modelos de simulação quanto os modelos RTL são derivados da mesma fonte C++, o que simplifica muito os processos de verificação e otimização do projeto. A eficácia de nossa metodologia de projeto é demonstrada em um processador RISC-V que executa o sistema operacional Linux em uma placa FPGA, alcançando um tempo de simulação significativamente curto do modelo de processador C++ original e do modelo C equivalente a RTL em comparação com um simulador RTL comercial.
Eiji YOSHIYA
the Tokyo Institute of Technology
Tomoya NAKANISHI
the Tokyo Institute of Technology
Tsuyoshi ISSHIKI
the Tokyo Institute of Technology
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Eiji YOSHIYA, Tomoya NAKANISHI, Tsuyoshi ISSHIKI, "Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 7, pp. 1061-1069, July 2022, doi: 10.1587/transfun.2021EAP1098.
Abstract: In Internet of Things (IoT) applications, system-on-chip (SoCs) with embedded processors are widely used. As an embedded processor, RISC-V, which is license-free and has an extensible instruction set, is receiving attention. However, designing such embedded processors requires an enormous effort to achieve a highly efficient microarchitecture in terms of performance, power consumption, and circuit area, as well as the design verification of running complex software, including modern operating systems such as Linux. In this paper, we propose a method for directly describing the RTL structure of a pipelined RISC-V processor with cache memories, a memory management unit (MMU), and an AXI bus interface using the C++ language. This pipelined processor C++ model serves as a functional simulator of the complete RISC-V core, whereas our C2RTL framework translates the processor C++ model into a cycle-accurate RTL description in the Verilog-HDL and RTL-equivalent C model. Our processor design methodology using the C2RTL framework is unique compared to other existing methodologies because both the simulation and RTL models are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor that runs Linux OS on an FPGA board, achieving a significantly short simulation time of the original C++ processor model and RTL-equivalent C model in comparison to a commercial RTL simulator.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021EAP1098/_p
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@ARTICLE{e105-a_7_1061,
author={Eiji YOSHIYA, Tomoya NAKANISHI, Tsuyoshi ISSHIKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework},
year={2022},
volume={E105-A},
number={7},
pages={1061-1069},
abstract={In Internet of Things (IoT) applications, system-on-chip (SoCs) with embedded processors are widely used. As an embedded processor, RISC-V, which is license-free and has an extensible instruction set, is receiving attention. However, designing such embedded processors requires an enormous effort to achieve a highly efficient microarchitecture in terms of performance, power consumption, and circuit area, as well as the design verification of running complex software, including modern operating systems such as Linux. In this paper, we propose a method for directly describing the RTL structure of a pipelined RISC-V processor with cache memories, a memory management unit (MMU), and an AXI bus interface using the C++ language. This pipelined processor C++ model serves as a functional simulator of the complete RISC-V core, whereas our C2RTL framework translates the processor C++ model into a cycle-accurate RTL description in the Verilog-HDL and RTL-equivalent C model. Our processor design methodology using the C2RTL framework is unique compared to other existing methodologies because both the simulation and RTL models are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor that runs Linux OS on an FPGA board, achieving a significantly short simulation time of the original C++ processor model and RTL-equivalent C model in comparison to a commercial RTL simulator.},
keywords={},
doi={10.1587/transfun.2021EAP1098},
ISSN={1745-1337},
month={July},}
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TY - JOUR
TI - Design Verification Methodology of Pipelined RISC-V Processor Using C2RTL Framework
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1061
EP - 1069
AU - Eiji YOSHIYA
AU - Tomoya NAKANISHI
AU - Tsuyoshi ISSHIKI
PY - 2022
DO - 10.1587/transfun.2021EAP1098
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 2022
AB - In Internet of Things (IoT) applications, system-on-chip (SoCs) with embedded processors are widely used. As an embedded processor, RISC-V, which is license-free and has an extensible instruction set, is receiving attention. However, designing such embedded processors requires an enormous effort to achieve a highly efficient microarchitecture in terms of performance, power consumption, and circuit area, as well as the design verification of running complex software, including modern operating systems such as Linux. In this paper, we propose a method for directly describing the RTL structure of a pipelined RISC-V processor with cache memories, a memory management unit (MMU), and an AXI bus interface using the C++ language. This pipelined processor C++ model serves as a functional simulator of the complete RISC-V core, whereas our C2RTL framework translates the processor C++ model into a cycle-accurate RTL description in the Verilog-HDL and RTL-equivalent C model. Our processor design methodology using the C2RTL framework is unique compared to other existing methodologies because both the simulation and RTL models are derived from the same C++ source, which greatly simplifies the design verification and optimization processes. The effectiveness of our design methodology is demonstrated on a RISC-V processor that runs Linux OS on an FPGA board, achieving a significantly short simulation time of the original C++ processor model and RTL-equivalent C model in comparison to a commercial RTL simulator.
ER -