The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este resumo apresenta um transmissor de modo duplo de 16/32 Gb/s incluindo um loop de calibração de linearidade para manter a linearidade de amplitude do driver SST. A detecção de linearidade e os correspondentes circuitos de alimentação mestre-escravo são projetados para implementar a arquitetura proposta. O transmissor proposto é fabricado em um processo FD-SOI de 22 nm. O loop de calibração de linearidade reduz os erros de pico de INL do transmissor em 50%, e o RLM aumenta de 92.4% para 98.5% quando o transmissor está no modo PAM4. A área do chip do transmissor é de 0.067 mm2, enquanto a parte proposta com linearidade aprimorada é 0.05 × 0.02 mm2 e o consumo total de energia é de 64.6 mW com uma fonte de alimentação de 1.1 V. O circuito de calibração de linearidade pode ser desconectado do circuito sem consumir energia extra.
Li DING
Shanghai Jiao Tong University
Jing JIN
Shanghai Jiao Tong University
Jianjun ZHOU
Shanghai Jiao Tong University
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Li DING, Jing JIN, Jianjun ZHOU, "A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 11, pp. 1443-1449, November 2022, doi: 10.1587/transfun.2021KEP0006.
Abstract: This brief presents A 16/32Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067mm2, while the proposed linearity enhanced part is 0.05×0.02mm2 and the total power consumption is 64.6mW with a 1.1V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021KEP0006/_p
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@ARTICLE{e105-a_11_1443,
author={Li DING, Jing JIN, Jianjun ZHOU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver},
year={2022},
volume={E105-A},
number={11},
pages={1443-1449},
abstract={This brief presents A 16/32Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067mm2, while the proposed linearity enhanced part is 0.05×0.02mm2 and the total power consumption is 64.6mW with a 1.1V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.},
keywords={},
doi={10.1587/transfun.2021KEP0006},
ISSN={1745-1337},
month={November},}
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TY - JOUR
TI - A 16/32Gbps Dual-Mode SerDes Transmitter with Linearity Enhanced SST Driver
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1443
EP - 1449
AU - Li DING
AU - Jing JIN
AU - Jianjun ZHOU
PY - 2022
DO - 10.1587/transfun.2021KEP0006
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 2022
AB - This brief presents A 16/32Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067mm2, while the proposed linearity enhanced part is 0.05×0.02mm2 and the total power consumption is 64.6mW with a 1.1V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.
ER -