The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A redução do consumo de energia é um fator crucial para tornar competitivos os projetos industriais, como os SoCs móveis. A escala de tensão (VS) é a técnica clássica, porém mais eficaz, que contribui para a redução quadrática de potência. Uma técnica de projeto recente chamada atribuição de folga com reconhecimento de ativação (ASA) aprimora a escala de tensão alocando a margem de temporização dos caminhos críticos com uma análise estocástica do tempo médio até a falha (MTTF). Enquanto isso, esse tratamento estocástico de erros de temporização é aceito em domínios de aplicação limitados, como o processamento de imagens. Este artigo propõe uma metodologia de otimização de projeto que atinge um projeto modal de tensão escalável (MWVS), garantindo nenhum erro de temporização em cada modo de operação. Este trabalho formula o projeto MWVS como um problema de otimização que minimiza o consumo geral de energia considerando a duração de cada modo, redução de tensão alcançável e sobrecarga de circuito acompanhada explicitamente, e explora o espaço de solução com o algoritmo downhill simplex que não requer derivação numérica e função objetivo frequente avaliações. Para obter uma solução, ou seja, um projeto, no processo de otimização, exploramos o fluxo de projeto multimodo multicanto em uma ferramenta comercial para realizar ASA modal com conjuntos de caminhos falsos dedicados a modos individuais. Aplicamos a metodologia de projeto proposta ao projeto RISC-V. Resultados experimentais mostram que a metodologia proposta economiza 13% a 20% mais energia em comparação com a abordagem VS convencional e atinge ganho de 8% a 15% com o ASA monomodo convencional. Descobrimos também que a identificação refinada de caminhos falsos, ciclo a ciclo, reduziu a potência de vazamento em 31% a 42%.
TaiYu CHENG
Osaka University
Yutaka MASUDA
Nagoya University
Jun NAGAYAMA
Socionext Inc.
Yoichi MOMIYAMA
Socionext Inc.
Jun CHEN
Osaka University
Masanori HASHIMOTO
Osaka University
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TaiYu CHENG, Yutaka MASUDA, Jun NAGAYAMA, Yoichi MOMIYAMA, Jun CHEN, Masanori HASHIMOTO, "Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization" in IEICE TRANSACTIONS on Fundamentals,
vol. E105-A, no. 3, pp. 497-508, March 2022, doi: 10.1587/transfun.2021VLP0006.
Abstract: Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique called activation-aware slack assignment (ASA) enhances the voltage-scaling by allocating the timing margin of critical paths with a stochastic mean-time-to-failure (MTTF) analysis. Meanwhile, such stochastic treatment of timing errors is accepted in limited application domains, such as image processing. This paper proposes a design optimization methodology that achieves a mode-wise voltage-scalable (MWVS) design guaranteeing no timing errors in each mode operation. This work formulates the MWVS design as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage lowering and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation and frequent objective function evaluations. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. We applied the proposed design methodology to RISC-V design. Experimental results show that the proposed methodology saves 13% to 20% more power compared to the conventional VS approach and attains 8% to 15% gain from the conventional single-mode ASA. We also found that cycle-by-cycle fine-grained false path identification reduced leakage power by 31% to 42%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2021VLP0006/_p
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@ARTICLE{e105-a_3_497,
author={TaiYu CHENG, Yutaka MASUDA, Jun NAGAYAMA, Yoichi MOMIYAMA, Jun CHEN, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization},
year={2022},
volume={E105-A},
number={3},
pages={497-508},
abstract={Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique called activation-aware slack assignment (ASA) enhances the voltage-scaling by allocating the timing margin of critical paths with a stochastic mean-time-to-failure (MTTF) analysis. Meanwhile, such stochastic treatment of timing errors is accepted in limited application domains, such as image processing. This paper proposes a design optimization methodology that achieves a mode-wise voltage-scalable (MWVS) design guaranteeing no timing errors in each mode operation. This work formulates the MWVS design as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage lowering and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation and frequent objective function evaluations. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. We applied the proposed design methodology to RISC-V design. Experimental results show that the proposed methodology saves 13% to 20% more power compared to the conventional VS approach and attains 8% to 15% gain from the conventional single-mode ASA. We also found that cycle-by-cycle fine-grained false path identification reduced leakage power by 31% to 42%.},
keywords={},
doi={10.1587/transfun.2021VLP0006},
ISSN={1745-1337},
month={March},}
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TY - JOUR
TI - Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 497
EP - 508
AU - TaiYu CHENG
AU - Yutaka MASUDA
AU - Jun NAGAYAMA
AU - Yoichi MOMIYAMA
AU - Jun CHEN
AU - Masanori HASHIMOTO
PY - 2022
DO - 10.1587/transfun.2021VLP0006
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E105-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2022
AB - Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique called activation-aware slack assignment (ASA) enhances the voltage-scaling by allocating the timing margin of critical paths with a stochastic mean-time-to-failure (MTTF) analysis. Meanwhile, such stochastic treatment of timing errors is accepted in limited application domains, such as image processing. This paper proposes a design optimization methodology that achieves a mode-wise voltage-scalable (MWVS) design guaranteeing no timing errors in each mode operation. This work formulates the MWVS design as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage lowering and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation and frequent objective function evaluations. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. We applied the proposed design methodology to RISC-V design. Experimental results show that the proposed methodology saves 13% to 20% more power compared to the conventional VS approach and attains 8% to 15% gain from the conventional single-mode ASA. We also found that cycle-by-cycle fine-grained false path identification reduced leakage power by 31% to 42%.
ER -