The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Propomos um caracterizador de biblioteca celular de código aberto. Recentemente, comunidades de design de silício gratuitas e de código aberto são atraídas por designers amadores, academias e indústrias. Esses projetos de silício de código aberto são suportados por EDAs gratuitos e de código aberto, no entanto, em nosso conhecimento, a cadeia de ferramentas carece de um caracterizador de biblioteca de células para usar células padrão originais no projeto de circuitos digitais. Este artigo propõe um caracterizador de biblioteca de células de código aberto que pode gerar modelos de temporização e modelos de potência de biblioteca de células padrão.
Shinichi NISHIZAWA
Waseda University
Toru NAKURA
Fukuoka University
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Shinichi NISHIZAWA, Toru NAKURA, "Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E106-A, no. 3, pp. 551-559, March 2023, doi: 10.1587/transfun.2022VLP0007.
Abstract: We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2022VLP0007/_p
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@ARTICLE{e106-a_3_551,
author={Shinichi NISHIZAWA, Toru NAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design},
year={2023},
volume={E106-A},
number={3},
pages={551-559},
abstract={We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.},
keywords={},
doi={10.1587/transfun.2022VLP0007},
ISSN={1745-1337},
month={March},}
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TY - JOUR
TI - Libretto: An Open Cell Timing Characterizer for Open Source VLSI Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 551
EP - 559
AU - Shinichi NISHIZAWA
AU - Toru NAKURA
PY - 2023
DO - 10.1587/transfun.2022VLP0007
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E106-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2023
AB - We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.
ER -