The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nos últimos anos, para atender às rígidas restrições de tempo de lançamento no mercado, tornou-se difícil para apenas uma empresa de design de semicondutores projetar um VLSI. Assim, as empresas de design compram núcleos de IP de fornecedores terceirizados e projetam apenas as peças necessárias. Por outro lado, como os núcleos IP têm a desvantagem de que a violação de direitos autorais pode ser facilmente cometida, o bloqueio lógico deve ser aplicado a eles. Os métodos de bloqueio lógico funcional usando TTLock são resilientes a ataques SAT, porém vulneráveis a ataques FALL. Além disso, é difícil projetar um bloqueio lógico baseado em TTLock no nível da porta. Este artigo propõe um método de bloqueio lógico, CRLock, baseado no ataque SAT e na resistência ao ataque FALL no nível de transferência de registradores. O CRLock é um método de bloqueio lógico para controladores em RTL no qual o projetista seleciona um padrão de entrada protegido e modifica o controlador com base no padrão de entrada de proteção. Nos resultados experimentais, aplicamos o CRLock aos circuitos de benchmark MCNC'91 e mostramos que todos os circuitos são resistentes a ataques SAT e FALL.
Masayoshi YOSHIMURA
Kyoto Sangyo University
Atsuya TSUJIKAWA
Nihon University
Toshinori HOSOKAWA
Nihon University
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Masayoshi YOSHIMURA, Atsuya TSUJIKAWA, Toshinori HOSOKAWA, "CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level" in IEICE TRANSACTIONS on Fundamentals,
vol. E107-A, no. 3, pp. 583-591, March 2024, doi: 10.1587/transfun.2023VLP0018.
Abstract: In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2023VLP0018/_p
Copiar
@ARTICLE{e107-a_3_583,
author={Masayoshi YOSHIMURA, Atsuya TSUJIKAWA, Toshinori HOSOKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level},
year={2024},
volume={E107-A},
number={3},
pages={583-591},
abstract={In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.},
keywords={},
doi={10.1587/transfun.2023VLP0018},
ISSN={1745-1337},
month={March},}
Copiar
TY - JOUR
TI - CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 583
EP - 591
AU - Masayoshi YOSHIMURA
AU - Atsuya TSUJIKAWA
AU - Toshinori HOSOKAWA
PY - 2024
DO - 10.1587/transfun.2023VLP0018
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E107-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2024
AB - In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.
ER -