The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve uma metodologia de projeto para D-Flip-Flop (DFF) com reconhecimento de variação de processo usando análise de regressão. Propomos usar uma análise de regressão para modelar as características de atraso do pior caso de um DFF sob variação do processo. Utilizamos a equação de regressão para ajuste da largura do transistor do DFF para melhorar seu desempenho de atraso no pior caso. A análise de regressão pode não apenas identificar os transistores críticos de desempenho dentro do DFF, mas também mostrar esses impactos no desempenho do atraso do DFF de forma quantitativa. A metodologia de projeto proposta é verificada usando simulação de Monte-Carlo. O resultado mostra que o método proposto consegue projetar um DFF que possui características de atraso semelhantes ou melhores em comparação com o DFF projetado por um projetista de células experiente.
Shinichi NISHIZAWA
Saitama University
Hidetoshi ONODERA
Kyoto University
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Shinichi NISHIZAWA, Hidetoshi ONODERA, "Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 12, pp. 2222-2230, December 2018, doi: 10.1587/transfun.E101.A.2222.
Abstract: This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.2222/_p
Copiar
@ARTICLE{e101-a_12_2222,
author={Shinichi NISHIZAWA, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis},
year={2018},
volume={E101-A},
number={12},
pages={2222-2230},
abstract={This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.},
keywords={},
doi={10.1587/transfun.E101.A.2222},
ISSN={1745-1337},
month={December},}
Copiar
TY - JOUR
TI - Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2222
EP - 2230
AU - Shinichi NISHIZAWA
AU - Hidetoshi ONODERA
PY - 2018
DO - 10.1587/transfun.E101.A.2222
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2018
AB - This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equation for transistor width tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
ER -