The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
À medida que a tecnologia de fabricação de dispositivos semicondutores evolui em direção a uma maior integração e redução do tamanho dos recursos, a lacuna entre o nível de defeito estimado na fase de projeto e o relatado para dispositivos fabricados tornou-se maior, tornando mais difícil controlar o custo total de fabricação, incluindo o custo de teste e o custo para falha de campo. Para estimar a cobertura de faltas com mais precisão considerando as probabilidades de ocorrência de faltas, propusemos uma estimativa ponderada de cobertura de faltas com base na área crítica correspondente a cada falta. Anteriormente, diferentes modelos de falhas eram tratados separadamente; portanto, a eficiência da compactação de padrões e o tempo de execução não foram otimizados. Neste estudo, propomos um esquema de geração de padrões de teste rápido que considera pontes ponderadas e cobertura de faltas abertas de forma integrada. O esquema proposto aplica a geração de padrões de teste em duas etapas, onde os padrões de teste gerados na segunda etapa que visam apenas falhas de ponte são reordenados com uma janela de busca de tamanho fixo, alcançando O(n) complexidade computacional. Resultados experimentais indicam que com 10% do tamanho inicial da falha alvo e um tamanho de janela pequeno e fixo, o esquema proposto atinge aproximadamente 100 vezes a redução do tempo de execução quando comparado ao reordenamento simples baseado em gananciosa, em troca de um incremento de contagem de padrões de cerca de 5%.
Masayuki ARAI
Nihon University
Shingo INUYAMA
Tokyo Metropolitan University
Kazuhiko IWASAKI
Tokyo Metropolitan University
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Masayuki ARAI, Shingo INUYAMA, Kazuhiko IWASAKI, "Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 12, pp. 2262-2270, December 2018, doi: 10.1587/transfun.E101.A.2262.
Abstract: As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.2262/_p
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@ARTICLE{e101-a_12_2262,
author={Masayuki ARAI, Shingo INUYAMA, Kazuhiko IWASAKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering},
year={2018},
volume={E101-A},
number={12},
pages={2262-2270},
abstract={As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.},
keywords={},
doi={10.1587/transfun.E101.A.2262},
ISSN={1745-1337},
month={December},}
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TY - JOUR
TI - Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2262
EP - 2270
AU - Masayuki ARAI
AU - Shingo INUYAMA
AU - Kazuhiko IWASAKI
PY - 2018
DO - 10.1587/transfun.E101.A.2262
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2018
AB - As semiconductor device manufacturing technology evolves toward higher integration and reduced feature size, the gap between the defect level estimated at the design stage and that reported for fabricated devices has become wider, making it more difficult to control total manufacturing cost including test cost and cost for field failure. To estimate fault coverage more precisely considering occurrence probabilities of faults, we have proposed weighted fault coverage estimation based on critical area corresponding to each fault. Previously different fault models were handled separately; thus, pattern compression efficiency and runtime were not optimized. In this study, we propose a fast test pattern generation scheme that considers weighted bridge and open fault coverage in an integrated manner. The proposed scheme applies two-step test pattern generation, wherein test patterns generated at second step that target only bridge faults are reordered with a search window of fixed size, achieving O(n) computational complexity. Experimental results indicate that with 10% of the initial target fault size and a fixed, small window size, the proposed scheme achieves approximately 100 times runtime reduction when compared to simple greedy-based reordering, in exchange for about 5% pattern count increment.
ER -